"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

Input Common-Mode Range
18-10
V
µ
– Input Offset Voltage –
V IO
100
80
60
40
20
0
–20
–40
–60
–80
–100
0 0.5 1 1.5 2 2.5 3
TLV245X
VCC =5 V
TA = 25° C
3.5 4
VIC – Common-Mode Input Voltage – V
4.5 5
Figure 18–6. Input Offset Voltage Changes with Input Common-Mode Voltage
When both transistors are conducting current the input bias currents have a tendency to
cancel, so in the range of ±1 V, the bias current is extremely low even when bipolar transistors
are used to make the op amp. Above this range, the PNP differential amplifier cuts
off so the full bias current requirement of the NPN transistor becomes apparent. The same
action happens below this range when the NPN differential amplifier cuts off. Notice that
the PNP bias current is significantly larger than the NPN bias current; this is expected because
NPN transistors have better gain characteristics than PNP transistors. The baseemitter
voltage of the NPN and PNP transistors is well matched because the magnitude
of the input offset voltage at the extremes is almost equal.
The bias current and offset voltage variation with input signal amplitude cause errors and
distortion of the input signal. Inserting a resistance equal to the parallel combination of
R F and R G into the positive op amp lead minimizes the effect of input bias current. The
resistor, R P, has the same voltage drop across it that the parallel combination of R F and
R G has, hence the bias current is converted to a common-mode voltage. The commonmode
voltage is normally in the µV-range because I IB is in the fractional nA range and R P
is in the tens of KΩ. The CMMR is approximately 60 dB, so the input bias current effect
is reduced to the nV range where it is insignificant compared to the offset voltage. The
input offset current is multiplied by R P, and it shows up as an input error. If the design can’t
tolerate these errors it is wise to switch to a CMOS op amp because its input currents are
in the pA range.
Another type of error creeps in when complementary differential amplifiers are used to
obtain DR, and this error is results from the different gain of the PNP and NPN transistors.