"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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Sine Wave Oscillator Circuits 15-10 the output and Z 1, V TEST is applied to Z 1, and V OUT is calculated. The positive feedback voltage, V +, is calculated first in Equations 15–6 through 15–8. Equation 15–6 shows the simple voltage divider at the noninverting input. Each term is then multiplied by (R 2C 2s + 1) and divided by R 2 to get Equation 15–7. V VTEST Z4 V Z3 Z4 TEST R2 R2C2s1 R 1 1 C1s V V TEST 1 1 R1C2S R1 R2 1 R2C1s C2 C1 R 2 R 2 C 2 s1 (15–6) (15–7) Substitute s = jω 0, where ω 0 is the oscillation frequency, ω 1 = 1/R 1C 2, and ω 2 = 1/R 2C 1 to get Equation 15–8. V V TEST 1 R 1 R 2 1 C2 j C1 0 1 2 0 (15–8) Some interesting relationships now become apparent. The capacitor in the zero, represented by ω 1, and the capacitor in the pole, represented by ω 2, must each contribute 90 of phase shift toward the 180 required for oscillation at ω 0. This requires that C 1 = C 2 and R 1 = R 2. Setting ω 1 and ω 2 equal to ω 0 cancels the frequency terms, ideally removing any change in amplitude with frequency since the pole and zero negate one another. An overall feedback factor of β = 1/3 is the result (Equation 15–9). V V TEST 1 1 R C R C j 0 0 1 3 j 0 0 0 0 1 3 (15–9) The gain of the negative feedback portion, A, of the circuit must then be set such that ⎟Aβ⎟ = 1, requiring A = 3. R F must be set to twice the value of R G to satisfy the condition. The op amp in Figure 15–7 is single supply, so a dc reference voltage, V REF, must be applied to bias the output for full-scale swing and minimal distortion. Applying V REF to the positive input through R 2 restricts dc current flow to the negative feedback leg of the circuit. V REF was set at 0.833V to bias the output at the midrail of the single supply, rail-to-rail input and output amplifier, or 2.5 V. See Cahpter 4 for details on dc biasing single-supply op amps. V REF is shorted to ground for split supply applications. The final circuit is shown in Figure 15–8, with component values selected to provide an oscillation frequency of ω 0 = 2πf 0, where f 0 = 1/(2πRC) = 15.9 kHz. The circuit oscillated at 1.57 kHz due to slightly varying component values with 2% distortion. This high value is due to the extensive clipping of the output signal at both supply rails, producing several
Sine Wave Oscillator Circuits large odd and even harmonics. The feedback resistor was then adjusted ±1%. Figure 15–9 shows the output voltage waveforms. The distortion grew as the saturation increased with increasing R F, and oscillations ceased when R F was decreased by more than 0.8%. RG 10 kΩ C RF = 2RG 20 kΩ +5 V _ TLV2471 VOUT + R 10 kΩ 10 nF C VREF 0.833 V 10 nF Figure 15–8. Final Wien Bridge Oscillator Circuit VCC = 5 V VREF = 0.833 V RG = 10.0 kΩ VOUT = 2 V/div Figure 15–9. Wien Bridge Output Waveforms + – Time = 500 µs/div R 10 kΩ Sine Wave Oscillators V+1% RF = 20.20 kΩ VI RF = 20 kΩ V–0.8% RF = 19.84 kΩ Applying nonlinear feedback can minimize the distortion inherent in the basic Wien bridge circuit. A nonlinear component such as an incandescent lamp can be substituted into 15-11
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Operational Amplifier Chapter 1: Th
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1-2 problem. It seems that circuits
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1-4 you are looking in the wrong pl
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Laws of Physics 2-2 V IR (2-1) In
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Current Divider Rule 2-4 put voltag
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Thevenin’s Theorem 2-6 V theorem
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Superposition 2.6 Superposition 2-8
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Transistor Amplifier 2-10 I C I B
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Transistor Amplifier 2-12 approxima
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Ideal Op Amp Assumptions 3-2 a hard
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The Inverting Op Amp 3-4 in a curre
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The Differential Amplifier 3.5 The
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Complex Feedback Networks 3-8 Break
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Capacitors Figure 3-10. Low-Pass Fi
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3-12
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Single Supply versus Dual Supply 4-
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Circuit Analysis 4-4 VREF VIN Figur
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Circuit Analysis 4-6 Four op amps w
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Simultaneous Equations 4.3 Simultan
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Simultaneous Equations 4-10 VOUT V
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Simultaneous Equations 4-12 VIN = 0
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Simultaneous Equations 4-14 m R F
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Simultaneous Equations 4.3.3 Case 3
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Simultaneous Equations 4-18 - Input
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Simultaneous Equations 4-20 |b| V
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Summary 4.4 Summary 4-22 Single-sup
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Block Diagram Math and Manipulation
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Block Diagram Math and Manipulation
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Feedback Equation and Stability 5.3
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Bode Analysis of Feedback Circuits
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Bode Analysis of Feedback Circuits
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Loop Gain Plots are the Key to Unde
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Loop Gain Plots are the Key to Unde
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References 5-16 M tangent 1 (2) (
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Review of the Canonical Equations 6
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Review of the Canonical Equations 6
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Inverting Op Amps 6-6 comparison al
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Differential Op Amps 6.5 Differenti
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6-10
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Internal Compensation 7-2 around in
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Internal Compensation 7-4 Damping R
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Internal Compensation AVD - Large-S
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External Compensation, Stability, a
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Dominant-Pole Compensation 7-10 VTH
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Gain Compensation 7-12 VOUT VIN a
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Lead Compensation 7-14 transfer fun
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Compensated Attenuator Applied to O
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Lead-Lag Compensation 7-18 FHASE (A
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Comparison of Compensation Schemes
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7-22
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Development of the Stability Equati
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The Noninverting CFA Figure 8-4. No
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The Inverting CFA 8-6 The current e
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Stability Analysis 8-8 The plot in
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Selection of the Feedback Resistor
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Stability and Feedback Capacitance
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Summary 8.11 Summary 8-14 A Z1 R
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Precision 9.2 Precision 9-2 The lon
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Bandwidth 9-4 A aR G R F R G (9-2
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Stability 9.4 Stability 9-6 Substit
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Equation Comparison 9-8 R G = 100
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9-10
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Characterization 10-2 Noise Signal
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Types of Noise 10.2.5 Noise Units 1
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Types of Noise 10-6 Shot noise is
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Types of Noise 10-8 Ith 4kTB R Wh
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Noise Colors Figure 10-4. Avalanche
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Op Amp Noise 10.4.3 Red/Brown Noise
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Op Amp Noise 10-14 E n Square it.
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Op Amp Noise 10.5.4 Inverting Op Am
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Op Amp Noise 10.5.6 Differential Op
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Putting It All Together 10-20 Vn Vn
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Putting It All Together 10-22 volta
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10-24
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Operational Amplifier Parameter Glo
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Additional Parameter Information 11
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12-2 The ADC selection is based on
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12-4 (A) 4 V 3 V ADC 0 V Sensor Out
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12.2 Transducer Types 12-6 This is
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12-8 some value, and R X is switche
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12-10 Resolvers and synchros are po
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12-12 6) Scan the transducer and AD
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12-14 the worst case excursions of
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Table 12-3. Op Amp Selection 12-16
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12-18 this yields m = 16.16. The re
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12-20 0.97R 1 VREF(MIN) VREF 50 m
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12-22 ply contribution is reduced b
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12-24
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Wireless Systems 13-2 Signal @ - 10
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Wireless Systems 13-4 900 MHz Figur
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Page 202 and 203: Selection of ADCs/DACs 13-8 Therefo
Page 204 and 205: Factors Influencing the Choice of O
Page 206 and 207: Anti-Aliasing Filters 13-12 anti-al
Page 208 and 209: Communication D/A Converter Reconst
Page 210 and 211: External Vref Circuits for ADCs/DAC
Page 212 and 213: High-Speed Analog Input Drive Circu
Page 214 and 215: High-Speed Analog Input Drive Circu
Page 216 and 217: References 13.9 References 13-22 [1
Page 218 and 219: Understanding the D/A Converter and
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Page 222 and 223: D/A Converter Error Budget 14-6 rat
Page 224 and 225: D/A Converter Error Budget 14-8 The
Page 226 and 227: D/A Converter Errors and Parameters
Page 234 and 235: Compensating For DAC Capacitance 14
Page 236 and 237: Increasing Op Amp Buffer Amplifier
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Page 242 and 243: Requirements for Oscillation 15-2 u
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Page 246 and 247: Active Element (Op Amp) Impact on t
Page 248 and 249: Analysis of the Oscillator Operatio
Page 252 and 253: Sine Wave Oscillator Circuits 15-12
Page 262 and 263: References 15.8 References 15-22 [1
Page 264 and 265: Fundamentals of Low-Pass Filters 16
Page 274 and 275: Low-Pass Filter Design 16-12 1st or
Page 276 and 277: Low-Pass Filter Design Example 16-1
Page 278 and 279: Low-Pass Filter Design 16-16 In ord
Page 280 and 281: Low-Pass Filter Design 16.3.2.2 Mul
Page 282 and 283: Low-Pass Filter Design Second Filte
Page 284 and 285: High-Pass Filter Design 16-22 |A|
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Band-Rejection Filter Design 16-38
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Band-Rejection Filter Design 16-40
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All-Pass Filter Design 16-42 2 i
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All-Pass Filter Design 16.7.1 First
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All-Pass Filter Design 16-46 V IN f
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Practical Design Hints 16-48 low-pa
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Practical Design Hints V IN 16-50 C
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Practical Design Hints 16-52 If thi
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Practical Design Hints 16-54 f T 1
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Filter Coefficient Tables Table 16-
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16-64
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General Considerations 17.1.3 Noise
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PCB Mechanical Construction 17-4 Te
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PCB Mechanical Construction 17.2.2.
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Grounding 17-8 DIGITAL + DIGITAL -
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Grounding 17-10 CONNECTOR POWER SUP
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The Frequency Characteristics of Pa
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Decoupling 17-20 For example, a 0.4
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Decoupling 17-22 EQUIVALENT SERIES
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Packages 17.7 Packages 17-24 N1 IN-
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Packages 17-26 IN1 + OUT1 IN2 IN3 O
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Summary 17-28 HALF SUPPLY GOOD _ +
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17-30
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Introduction 18-2 swing at V CC = 5
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Dynamic Range 18-4 VIN VnR Figure 1
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Input Common-Mode Range 18-6 sible
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Input Common-Mode Range 18-8 VCC GN
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Input Common-Mode Range 18-10 V µ
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Shutdown and Low Current Drain 18-1
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Transducer to ADC Analog Interface
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DAC to Actuator Analog Interface 18
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DAC to Actuator Analog Interface 18
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Comparison of Op Amps 18-20 When DA
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Summary 18.11 Summary 18-22 Always
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"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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