"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

Analog Output Voltage
Digital
Change
Glitch
Figure 14–13. D/A Settling Time
Settling Time — tS
Delay Time
Slew Rate
Error Band
D/A Converter Errors and Parameters
Final Value
When an output buffer op amp is used with a D/A, it becomes a part of the settling time/
conversion rate calculations.
Related to the settling time is a glitch response that occurs when the digital code changes
state. Even though this effect is transitory in nature, it can result in noise or harmonics
when used in fast AC applications. The best way of reducing the glitch is to properly decouple
the D/A and op amp buffer (see Chapter 17). In extreme cases, a deglitching circuit
may be needed (Figure 14–14).
BUFFER OUT
CONTROL
Figure 14–14. D/A Deglitch Circuit
R
R
_
+
CHOLD
Interfacing D/A Converters to Loads
t
DEGLITCHED
OUTPUT
This technique relies on the software designer to balance the timing of the control signal
so it activates the hold function right before the D/A input code changes, then releases
the hold right after the code has changed. The selection of C HOLD is critical — it must hold
the buffer output without droop and without compromising system bandwidth.
14-17