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"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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Table 12–3. <strong>Op</strong> Amp Selection<br />

12-16<br />

DESIGN<br />

SPECIFICATION<br />

ESTIMATED VALUE<br />

RIN <strong>10</strong>6 (13) Ω <strong>10</strong>12 Ω<br />

CANDIDATE OP AMP:<br />

TLV247X<br />

VTOV 350 mV to 700 mV –0.2 V to 5.2 V<br />

ROUT<br />

1.8 Ω<br />

VINADC 0 V to 4 V 0.15 V to 4.85 V<br />

VOS ––– 2.2 mV<br />

IB ––– <strong>10</strong>0 pA<br />

VN<br />

–––<br />

28 nV<br />

Hz<br />

IN<br />

–––<br />

0.39 pA<br />

Hz<br />

Analog noise ––– <strong>10</strong> mV<br />

kSVR ––– 63 dB<br />

<strong>The</strong>re should be almost no error from R IN because <strong>the</strong> transducer output impedance is<br />

very low. <strong>The</strong> high side of <strong>the</strong> op amp’s output voltage sw<strong>in</strong>g (4.85 V) is much higher than<br />

<strong>the</strong> ADC <strong>in</strong>put voltage (4 V). <strong>The</strong> low side of <strong>the</strong> op amp’s output voltage sw<strong>in</strong>g (0.185 V)<br />

is less than <strong>the</strong> ADC <strong>in</strong>put voltage sw<strong>in</strong>g (0 V). <strong>The</strong> ADC <strong>in</strong>put circuit is 20 kΩ and that<br />

doesn’t load <strong>the</strong> op amp output stage, so <strong>the</strong> op amp output voltage sw<strong>in</strong>g is very close<br />

to <strong>the</strong> ADC <strong>in</strong>put voltage range. R OUT should present no problems act<strong>in</strong>g as a voltage divider<br />

with <strong>the</strong> ADC <strong>in</strong>put resistance. V OS and I IB create offset voltages that add to <strong>the</strong> reference<br />

offset voltage, and <strong>the</strong>y have to be adjusted out as a group. <strong>The</strong> system noise<br />

overshadows <strong>the</strong> op amp noise, thus <strong>the</strong> op amp noise is accepted unless later calculation<br />

prove o<strong>the</strong>rwise.<br />

12.9 Amplifier Circuit Design<br />

Enough <strong>in</strong>formation exists for <strong>the</strong> AIA to be designed. <strong>The</strong> TLV247X op amp is selected<br />

because it meets all <strong>the</strong> system requirements. <strong>The</strong> first step <strong>in</strong> <strong>the</strong> design is to determ<strong>in</strong>e<br />

<strong>the</strong> AIA <strong>in</strong>put and output voltages, and this has already been done. <strong>The</strong>se voltages are<br />

taken from Tables 12–1 and 12–2, and repeated here as Table 12–4.<br />

Table 12–4. AIA Input and Output Voltages<br />

INPUT VOLTAGE OUTPUT VOLTAGES<br />

VIN1 = 650 mV VOUT1 = 0 V 1st pair of data po<strong>in</strong>ts<br />

VIN2 = 400 mV VOUT2 = 4 V 2nd pair of data po<strong>in</strong>ts<br />

<strong>The</strong> equation of an op amp is <strong>the</strong> equation of a straight l<strong>in</strong>e as given <strong>in</strong> Equation 12–14.

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