"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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12-14 the worst case excursions of I D (Equations 12–10 and 12–11). The resistors are assumed to have a 2% tolerance in these calculations. The extra 1% allows for temperature changes, vibration, and life. Three percent tolerances would have been used if the electronics’ ambient temperature range were larger. I D(MIN) V REF(MIN) R B2(MAX) I D(MAX) V REF(MAX) R B2(MIN) 2.47 0.025 0.007 1.02 (1.24) 2.52 0.025 0.007 0.98 (1.24) 1.93 mA 2.10 mA (12–10) (12–11) The bias current extremes do not exceed the transducer bias current requirements, so the transducer will meet the specifications advertised. The converter is 12 bits and the full-scale voltage is assumed to be 5 V, so the value of an LSB is calculated in Equation 12–12. The nominal transducer output voltage is 550 mV at an ambient temperature of 25°C. At –25°C, the transducer output voltage is 550 mV+ (–2 mV/°C)(–50°C) = 650 mV. At 125°C, the transducer output voltage is 550 mV + (–2 mV°C)(75°C) = 400 mV. This data is tabulated in Table 12–1. LSB FSV 5 1.22 mV 2N 212 Table 12–1. Transducer Output Voltage TRANSDUCER TEMPERATURE TRANSDUCER OUTPUT VOLTAGE ANALOG INTERFACE AMPLIFIER INPUT VOLTAGE –25°C 650 mV VIN1 = 650 mV 25°C 550 mV 550 mV 100°C 400 mV VIN2 = 400 mV (12–12) The steady state (V TOS) offset voltage is ± 50 mV, thus transducer output voltage (V TOV) ranges from 350 mV to 700 mV. The offset voltage is stripped out by the adjustments in the AIA, so it is not of any concern here. V TOS spans 100 mV, thus it is a 100 mV/1.22 mV/ bit = 82 bit error unless it is adjusted out. The output impedance of the transducer is equivalent to the resistance of a forward biased diode (Equation 12–13). R D 26 I 26 2 13 (12–13) At this stage of the design there are two parameters that influence the accuracy of the measurement, and they are the temperature coefficient of the transducer and the output
impedance of the transducer. The temperature transducer has been biased correctly, thus its temperature coefficient should be the advertised value of –2 mV/ °C. The output impedance of the transducer forms a voltage divider with the input resistance of the AIA, but this error can’t be calculated until the AIA is selected. The final transducer error contribution is that portion of the V TOS that can’t be adjusted out, and this error is determined during the AIA design. 12.7 ADC Characterization This particular ADC was selected because it has a multiplexer and it enables different modes of operation. The temperature measurement is done in the single-shot mode because this mode allows the user to set the charge time at the input to the converter. During charging, the ADC’s input resistance is low, but after the ADC input is charged the input resistance rises to 20 kΩ. This high input resistance does not load the AIA output circuit, thus the AIA achieves full rail-to-rail output voltage swing. The internal reference is used in this application, and the reference sets the input voltage span required to obtain full accuracy for the ADC. Using the internal reference, the input voltage span is 0 V to 4 V. The offset voltage (V ADCOS) is ± 150 mV, and the voltage drift is 40 PPM/°C. The voltage drift over the full temperature range is 40 PPM/°C(20°C) = 800 PPM. There are 244 PPM/LSB in a 12-bit converter, so the drift voltage error is 800/244 ≈ 4 bits error. The ADC output is full scale (all bits 1) when the input voltage is 4 V, and it is zero (all bits 0) when the input voltage is 0 V. This data is tabulated in Table 12–2. Because the full scale output voltage has changed to 4 volts the LSB is calculated to be 4/(2 12) = 976.6 µV/bit. Table 12–2. ADC Input Voltage 12.8 Op Amp Selection ADC INPUT VOLTAGE DIGITAL OUTPUT 0 V 000000000000 VOUT1 = 0 V 4 V 111111111111 VOUT2 = 4 V ANALOG INTERFACE AMPLIFIER OUTPUT VOLTAGE It is time to select the op amp, and the easiest way to do this is to list the known specifications or requirements, list a candidate op amp’s specifications, and calculated the projected error that the candidate op amp yields. 12-15
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Operational Amplifier Chapter 1: Th
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1-2 problem. It seems that circuits
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1-4 you are looking in the wrong pl
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Laws of Physics 2-2 V IR (2-1) In
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Current Divider Rule 2-4 put voltag
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Thevenin’s Theorem 2-6 V theorem
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Superposition 2.6 Superposition 2-8
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Transistor Amplifier 2-10 I C I B
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Transistor Amplifier 2-12 approxima
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Ideal Op Amp Assumptions 3-2 a hard
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The Inverting Op Amp 3-4 in a curre
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The Differential Amplifier 3.5 The
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Complex Feedback Networks 3-8 Break
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Capacitors Figure 3-10. Low-Pass Fi
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3-12
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Single Supply versus Dual Supply 4-
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Circuit Analysis 4-4 VREF VIN Figur
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Circuit Analysis 4-6 Four op amps w
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Simultaneous Equations 4.3 Simultan
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Simultaneous Equations 4-10 VOUT V
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Simultaneous Equations 4-12 VIN = 0
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Simultaneous Equations 4-14 m R F
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Simultaneous Equations 4.3.3 Case 3
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Simultaneous Equations 4-18 - Input
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Simultaneous Equations 4-20 |b| V
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Summary 4.4 Summary 4-22 Single-sup
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Block Diagram Math and Manipulation
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Block Diagram Math and Manipulation
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Feedback Equation and Stability 5.3
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Bode Analysis of Feedback Circuits
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Bode Analysis of Feedback Circuits
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Loop Gain Plots are the Key to Unde
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Loop Gain Plots are the Key to Unde
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References 5-16 M tangent 1 (2) (
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Review of the Canonical Equations 6
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Review of the Canonical Equations 6
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Inverting Op Amps 6-6 comparison al
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Differential Op Amps 6.5 Differenti
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6-10
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Internal Compensation 7-2 around in
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Internal Compensation 7-4 Damping R
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Internal Compensation AVD - Large-S
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External Compensation, Stability, a
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Dominant-Pole Compensation 7-10 VTH
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Gain Compensation 7-12 VOUT VIN a
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Lead Compensation 7-14 transfer fun
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Compensated Attenuator Applied to O
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Lead-Lag Compensation 7-18 FHASE (A
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Comparison of Compensation Schemes
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7-22
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Development of the Stability Equati
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The Noninverting CFA Figure 8-4. No
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The Inverting CFA 8-6 The current e
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Stability Analysis 8-8 The plot in
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Selection of the Feedback Resistor
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Stability and Feedback Capacitance
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Summary 8.11 Summary 8-14 A Z1 R
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Precision 9.2 Precision 9-2 The lon
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Bandwidth 9-4 A aR G R F R G (9-2
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Stability 9.4 Stability 9-6 Substit
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Equation Comparison 9-8 R G = 100
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9-10
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Characterization 10-2 Noise Signal
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Types of Noise 10.2.5 Noise Units 1
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Types of Noise 10-6 Shot noise is
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Types of Noise 10-8 Ith 4kTB R Wh
Page 134 and 135: Noise Colors Figure 10-4. Avalanche
Page 136 and 137: Op Amp Noise 10.4.3 Red/Brown Noise
Page 138 and 139: Op Amp Noise 10-14 E n Square it.
Page 140 and 141: Op Amp Noise 10.5.4 Inverting Op Am
Page 142 and 143: Op Amp Noise 10.5.6 Differential Op
Page 144 and 145: Putting It All Together 10-20 Vn Vn
Page 146 and 147: Putting It All Together 10-22 volta
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Page 150 and 151: Operational Amplifier Parameter Glo
Page 156 and 157: Additional Parameter Information 11
Page 172 and 173: 12-2 The ADC selection is based on
Page 174 and 175: 12-4 (A) 4 V 3 V ADC 0 V Sensor Out
Page 176 and 177: 12.2 Transducer Types 12-6 This is
Page 178 and 179: 12-8 some value, and R X is switche
Page 180 and 181: 12-10 Resolvers and synchros are po
Page 182 and 183: 12-12 6) Scan the transducer and AD
Page 186 and 187: Table 12-3. Op Amp Selection 12-16
Page 188 and 189: 12-18 this yields m = 16.16. The re
Page 190 and 191: 12-20 0.97R 1 VREF(MIN) VREF 50 m
Page 192 and 193: 12-22 ply contribution is reduced b
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Page 196 and 197: Wireless Systems 13-2 Signal @ - 10
Page 198 and 199: Wireless Systems 13-4 900 MHz Figur
Page 200 and 201: Selection of ADCs/DACs 13.3 Selecti
Page 202 and 203: Selection of ADCs/DACs 13-8 Therefo
Page 204 and 205: Factors Influencing the Choice of O
Page 206 and 207: Anti-Aliasing Filters 13-12 anti-al
Page 208 and 209: Communication D/A Converter Reconst
Page 210 and 211: External Vref Circuits for ADCs/DAC
Page 212 and 213: High-Speed Analog Input Drive Circu
Page 214 and 215: High-Speed Analog Input Drive Circu
Page 216 and 217: References 13.9 References 13-22 [1
Page 218 and 219: Understanding the D/A Converter and
Page 220 and 221: Understanding the D/A Converter and
Page 222 and 223: D/A Converter Error Budget 14-6 rat
Page 224 and 225: D/A Converter Error Budget 14-8 The
Page 226 and 227: D/A Converter Errors and Parameters
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Compensating For DAC Capacitance 14
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Increasing Op Amp Buffer Amplifier
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Increasing Op Amp Buffer Amplifier
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14-24
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Requirements for Oscillation 15-2 u
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Gain in the Oscillator 15-4 The fre
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Active Element (Op Amp) Impact on t
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Analysis of the Oscillator Operatio
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Sine Wave Oscillator Circuits 15-10
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References 15.8 References 15-22 [1
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Fundamentals of Low-Pass Filters 16
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Low-Pass Filter Design 16-12 1st or
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Low-Pass Filter Design Example 16-1
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Low-Pass Filter Design 16-16 In ord
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Low-Pass Filter Design 16.3.2.2 Mul
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Low-Pass Filter Design Second Filte
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High-Pass Filter Design 16-22 |A|
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High-Pass Filter Design 16-24 To di
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High-Pass Filter Design 16-26 Throu
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Band-Pass Filter Design 16-28 |A| [
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Band-Pass Filter Design 16-30 The g
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Band-Pass Filter Design 16-32 out a
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Band-Pass Filter Design 16-34 After
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Band-Rejection Filter Design 16-36
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All-Pass Filter Design 16-42 2 i
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All-Pass Filter Design 16.7.1 First
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All-Pass Filter Design 16-46 V IN f
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Practical Design Hints 16-48 low-pa
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Practical Design Hints V IN 16-50 C
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Practical Design Hints 16-52 If thi
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Practical Design Hints 16-54 f T 1
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Filter Coefficient Tables Table 16-
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16-64
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General Considerations 17.1.3 Noise
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PCB Mechanical Construction 17-4 Te
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PCB Mechanical Construction 17.2.2.
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Grounding 17-8 DIGITAL + DIGITAL -
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Grounding 17-10 CONNECTOR POWER SUP
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The Frequency Characteristics of Pa
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Decoupling 17-20 For example, a 0.4
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Decoupling 17-22 EQUIVALENT SERIES
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Packages 17.7 Packages 17-24 N1 IN-
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Packages 17-26 IN1 + OUT1 IN2 IN3 O
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Summary 17-28 HALF SUPPLY GOOD _ +
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17-30
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Introduction 18-2 swing at V CC = 5
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Dynamic Range 18-4 VIN VnR Figure 1
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Input Common-Mode Range 18-6 sible
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Input Common-Mode Range 18-8 VCC GN
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Input Common-Mode Range 18-10 V µ
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Shutdown and Low Current Drain 18-1
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Transducer to ADC Analog Interface
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DAC to Actuator Analog Interface 18
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DAC to Actuator Analog Interface 18
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Comparison of Op Amps 18-20 When DA
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Summary 18.11 Summary 18-22 Always
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18-24
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"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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