"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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Transistor Amplifier 2-12 approximately R C/R E1 because C E shorts out R E2 at high frequencies, so we can write Equation 2–38. R E1 R C G 400 4 100 R E2 R E R E1 400 100 300 (2–38) (2–39) The capacitor selection depends on the frequency response required for the amplifier, but 10 µF for C IN and 1000 µF for C E suffice for a starting point.
Development of the Ideal Op Amp Equations 3.1 Ideal Op Amp Assumptions Ron Mancini Chapter 3 The name Ideal Op Amp is applied to this and similar analysis because the salient parameters of the op amp are assumed to be perfect. There is no such thing as an ideal op amp, but present day op amps come so close to ideal that Ideal Op Amp analysis approaches actual analysis. Op amps depart from the ideal in two ways. First, dc parameters such as input offset voltage are large enough to cause departure from the ideal. The ideal assumes that input offset voltage is zero. Second, ac parameters such as gain are a function of frequency, so they go from large values at dc to small values at high frequencies. This assumption simplifies the analysis, thus it clears the path for insight. It is so much easier to see the forest when the brush and huge trees are cleared away. Although the ideal op amp analysis makes use of perfect parameters, the analysis is often valid because some op amps approach perfection. In addition, when working at low frequencies, several kHz, the ideal op amp analysis produces accurate answers. Voltage feedback op amps are covered in this chapter, and current feedback op amps are covered in Chapter 8. Several assumptions have to be made before the ideal op amp analysis can proceed. First, assume that the current flow into the input leads of the op amp is zero. This assumption is almost true in FET op amps where input currents can be less than a pA, but this is not always true in bipolar high-speed op amps where tens of µA input currents are found. Second, the op amp gain is assumed to be infinite, hence it drives the output voltage to any value to satisfy the input conditions. This assumes that the op amp output voltage can achieve any value. In reality, saturation occurs when the output voltage comes close to a power supply rail, but reality does not negate the assumption, it only bounds it. Also, implicit in the infinite gain assumption is the need for zero input signal. The gain drives the output voltage until the voltage between the input leads (the error voltage) is zero. This leads to the third assumption that the voltage between the input leads is zero. The implication of zero voltage between the input leads means that if one input is tied to 3-1
Page 1: Operational Amplifier Chapter 1: Th
Page 4 and 5: 1-2 problem. It seems that circuits
Page 6 and 7: 1-4 you are looking in the wrong pl
Page 8 and 9: Laws of Physics 2-2 V IR (2-1) In
Page 10 and 11: Current Divider Rule 2-4 put voltag
Page 12 and 13: Thevenin’s Theorem 2-6 V theorem
Page 14 and 15: Superposition 2.6 Superposition 2-8
Page 16 and 17: Transistor Amplifier 2-10 I C I B
Page 20 and 21: Ideal Op Amp Assumptions 3-2 a hard
Page 22 and 23: The Inverting Op Amp 3-4 in a curre
Page 24 and 25: The Differential Amplifier 3.5 The
Page 26 and 27: Complex Feedback Networks 3-8 Break
Page 28 and 29: Capacitors Figure 3-10. Low-Pass Fi
Page 30 and 31: 3-12
Page 32 and 33: Single Supply versus Dual Supply 4-
Page 34 and 35: Circuit Analysis 4-4 VREF VIN Figur
Page 36 and 37: Circuit Analysis 4-6 Four op amps w
Page 38 and 39: Simultaneous Equations 4.3 Simultan
Page 40 and 41: Simultaneous Equations 4-10 VOUT V
Page 42 and 43: Simultaneous Equations 4-12 VIN = 0
Page 44 and 45: Simultaneous Equations 4-14 m R F
Page 46 and 47: Simultaneous Equations 4.3.3 Case 3
Page 48 and 49: Simultaneous Equations 4-18 - Input
Page 50 and 51: Simultaneous Equations 4-20 |b| V
Page 52 and 53: Summary 4.4 Summary 4-22 Single-sup
Page 54 and 55: Block Diagram Math and Manipulation
Page 56 and 57: Block Diagram Math and Manipulation
Page 58 and 59: Feedback Equation and Stability 5.3
Page 60 and 61: Bode Analysis of Feedback Circuits
Page 62 and 63: Bode Analysis of Feedback Circuits
Page 64 and 65: Loop Gain Plots are the Key to Unde
Page 66 and 67: Loop Gain Plots are the Key to Unde
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References 5-16 M tangent 1 (2) (
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Review of the Canonical Equations 6
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Review of the Canonical Equations 6
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Inverting Op Amps 6-6 comparison al
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Differential Op Amps 6.5 Differenti
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6-10
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Internal Compensation 7-2 around in
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Internal Compensation 7-4 Damping R
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Internal Compensation AVD - Large-S
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External Compensation, Stability, a
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Dominant-Pole Compensation 7-10 VTH
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Gain Compensation 7-12 VOUT VIN a
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Lead Compensation 7-14 transfer fun
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Compensated Attenuator Applied to O
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Lead-Lag Compensation 7-18 FHASE (A
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Comparison of Compensation Schemes
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7-22
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Development of the Stability Equati
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The Noninverting CFA Figure 8-4. No
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The Inverting CFA 8-6 The current e
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Stability Analysis 8-8 The plot in
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Selection of the Feedback Resistor
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Stability and Feedback Capacitance
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Summary 8.11 Summary 8-14 A Z1 R
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Precision 9.2 Precision 9-2 The lon
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Bandwidth 9-4 A aR G R F R G (9-2
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Stability 9.4 Stability 9-6 Substit
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Equation Comparison 9-8 R G = 100
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9-10
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Characterization 10-2 Noise Signal
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Types of Noise 10.2.5 Noise Units 1
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Types of Noise 10-6 Shot noise is
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Types of Noise 10-8 Ith 4kTB R Wh
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Noise Colors Figure 10-4. Avalanche
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Op Amp Noise 10.4.3 Red/Brown Noise
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Op Amp Noise 10-14 E n Square it.
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Op Amp Noise 10.5.4 Inverting Op Am
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Op Amp Noise 10.5.6 Differential Op
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Putting It All Together 10-20 Vn Vn
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Putting It All Together 10-22 volta
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10-24
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Operational Amplifier Parameter Glo
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Additional Parameter Information 11
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12-2 The ADC selection is based on
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12-4 (A) 4 V 3 V ADC 0 V Sensor Out
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12.2 Transducer Types 12-6 This is
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12-8 some value, and R X is switche
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12-10 Resolvers and synchros are po
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12-12 6) Scan the transducer and AD
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12-14 the worst case excursions of
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Table 12-3. Op Amp Selection 12-16
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12-18 this yields m = 16.16. The re
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12-20 0.97R 1 VREF(MIN) VREF 50 m
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12-22 ply contribution is reduced b
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12-24
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Wireless Systems 13-2 Signal @ - 10
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Wireless Systems 13-4 900 MHz Figur
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Selection of ADCs/DACs 13.3 Selecti
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Selection of ADCs/DACs 13-8 Therefo
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Factors Influencing the Choice of O
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Anti-Aliasing Filters 13-12 anti-al
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Communication D/A Converter Reconst
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External Vref Circuits for ADCs/DAC
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High-Speed Analog Input Drive Circu
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High-Speed Analog Input Drive Circu
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References 13.9 References 13-22 [1
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Understanding the D/A Converter and
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Understanding the D/A Converter and
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D/A Converter Error Budget 14-6 rat
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D/A Converter Error Budget 14-8 The
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D/A Converter Errors and Parameters
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Compensating For DAC Capacitance 14
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Increasing Op Amp Buffer Amplifier
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Increasing Op Amp Buffer Amplifier
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14-24
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Requirements for Oscillation 15-2 u
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Gain in the Oscillator 15-4 The fre
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Active Element (Op Amp) Impact on t
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Analysis of the Oscillator Operatio
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Sine Wave Oscillator Circuits 15-10
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References 15.8 References 15-22 [1
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Fundamentals of Low-Pass Filters 16
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Low-Pass Filter Design 16-12 1st or
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Low-Pass Filter Design Example 16-1
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Low-Pass Filter Design 16-16 In ord
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Low-Pass Filter Design 16.3.2.2 Mul
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Low-Pass Filter Design Second Filte
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High-Pass Filter Design 16-22 |A|
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High-Pass Filter Design 16-24 To di
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High-Pass Filter Design 16-26 Throu
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Band-Pass Filter Design 16-28 |A| [
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Band-Pass Filter Design 16-30 The g
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Band-Pass Filter Design 16-32 out a
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Band-Pass Filter Design 16-34 After
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Band-Rejection Filter Design 16-36
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All-Pass Filter Design 16-42 2 i
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All-Pass Filter Design 16.7.1 First
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All-Pass Filter Design 16-46 V IN f
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Practical Design Hints 16-48 low-pa
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Practical Design Hints V IN 16-50 C
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Practical Design Hints 16-52 If thi
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Practical Design Hints 16-54 f T 1
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Filter Coefficient Tables Table 16-
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16-64
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General Considerations 17.1.3 Noise
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PCB Mechanical Construction 17-4 Te
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PCB Mechanical Construction 17.2.2.
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Grounding 17-8 DIGITAL + DIGITAL -
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Grounding 17-10 CONNECTOR POWER SUP
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The Frequency Characteristics of Pa
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Decoupling 17-20 For example, a 0.4
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Decoupling 17-22 EQUIVALENT SERIES
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Packages 17.7 Packages 17-24 N1 IN-
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Packages 17-26 IN1 + OUT1 IN2 IN3 O
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Summary 17-28 HALF SUPPLY GOOD _ +
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17-30
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Introduction 18-2 swing at V CC = 5
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Dynamic Range 18-4 VIN VnR Figure 1
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Input Common-Mode Range 18-6 sible
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Input Common-Mode Range 18-8 VCC GN
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Input Common-Mode Range 18-10 V µ
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Shutdown and Low Current Drain 18-1
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Transducer to ADC Analog Interface
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DAC to Actuator Analog Interface 18
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DAC to Actuator Analog Interface 18
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Comparison of Op Amps 18-20 When DA
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Summary 18.11 Summary 18-22 Always
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18-24
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"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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