"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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Additional Parameter Information 11-20 GBW specifies the gain-bandwidth product of the op amp in an open loop configuration and the output loaded: GBW A VD f (11–5) GBW is constant for voltage-feedback amplifiers. It does not have much meaning for current-feedback amplifiers because there is not a linear relationship between gain and bandwidth. Phase margin at unity gain (φ m) is the difference between the amount of phase shift a signal experiences through the op amp at unity gain and 180: m 180° @B1 Gain margin is the difference between unity gain and the gain at 180 phase shift: Gain margin 1 Gain @180° phase shift (11–6) (11–7) Maximum output-swing bandwidth (B OM) specifies the bandwidth over which the output is above a specified value: B OM f MAX, while V O V MIN (11–8) The limiting factor for B OM is slew rate. As the frequency gets higher and higher the output becomes slew rate limited and can not respond quickly enough to maintain the specified output voltage swing. In order to make the op amp stable, capacitor, C C, is purposely fabricated on chip in the second stage (Figure 11–8). This type of frequency compensation is termed dominant pole compensation. The idea is to cause the open-loop gain of the op amp to roll off to unity before the output phase shifts by 180. Remember that Figure 11–8 is very simplified, and there are other frequency shaping elements within a real op amp. Figure 11–11 shows a typical gain vs. frequency plot for an internally compensated op amp as normally presented in a Texas Instruments data sheet. As noted earlier, A VD falls off with frequency. A VD (and thus B 1 or GBW) is a design issue when precise gain is required of a specific frequency band. Phase margin (φ m) and gain margin (A m) are different ways of specifying the stability of the circuit. Since rail-to-rail output op amps have higher output impedance, a significant phase shift is seen when driving capacitive loads. This extra phase shift erodes the phase margin, and for this reason most CMOS op amps with rail-to-rail outputs have limited ability to drive capacitive loads.
AVD — dB Phase — ° 120 100 80 60 40 20 0 –20 0 45 90 135 180 225 0 10 100 Dominant Pole φm Frequency — Hz B1 1 k 10 k 100 k 1 M 10 M Figure 11–11.Voltage Amplification and Phase Shift vs. Frequency Additional Parameter Information Gain Margin Understanding Op Amp Parameters 11-21
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Operational Amplifier Chapter 1: Th
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1-2 problem. It seems that circuits
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1-4 you are looking in the wrong pl
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Laws of Physics 2-2 V IR (2-1) In
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Current Divider Rule 2-4 put voltag
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Thevenin’s Theorem 2-6 V theorem
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Superposition 2.6 Superposition 2-8
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Transistor Amplifier 2-10 I C I B
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Transistor Amplifier 2-12 approxima
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Ideal Op Amp Assumptions 3-2 a hard
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The Inverting Op Amp 3-4 in a curre
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The Differential Amplifier 3.5 The
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Complex Feedback Networks 3-8 Break
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Capacitors Figure 3-10. Low-Pass Fi
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3-12
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Single Supply versus Dual Supply 4-
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Circuit Analysis 4-4 VREF VIN Figur
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Circuit Analysis 4-6 Four op amps w
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Simultaneous Equations 4.3 Simultan
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Simultaneous Equations 4-10 VOUT V
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Simultaneous Equations 4-12 VIN = 0
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Simultaneous Equations 4-14 m R F
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Simultaneous Equations 4.3.3 Case 3
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Simultaneous Equations 4-18 - Input
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Simultaneous Equations 4-20 |b| V
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Summary 4.4 Summary 4-22 Single-sup
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Block Diagram Math and Manipulation
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Block Diagram Math and Manipulation
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Feedback Equation and Stability 5.3
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Bode Analysis of Feedback Circuits
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Bode Analysis of Feedback Circuits
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Loop Gain Plots are the Key to Unde
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Loop Gain Plots are the Key to Unde
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References 5-16 M tangent 1 (2) (
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Review of the Canonical Equations 6
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Review of the Canonical Equations 6
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Inverting Op Amps 6-6 comparison al
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Differential Op Amps 6.5 Differenti
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6-10
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Internal Compensation 7-2 around in
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Internal Compensation 7-4 Damping R
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Internal Compensation AVD - Large-S
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External Compensation, Stability, a
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Dominant-Pole Compensation 7-10 VTH
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Gain Compensation 7-12 VOUT VIN a
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Lead Compensation 7-14 transfer fun
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Compensated Attenuator Applied to O
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Lead-Lag Compensation 7-18 FHASE (A
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Comparison of Compensation Schemes
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7-22
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Development of the Stability Equati
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The Noninverting CFA Figure 8-4. No
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The Inverting CFA 8-6 The current e
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Stability Analysis 8-8 The plot in
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Selection of the Feedback Resistor
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Stability and Feedback Capacitance
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Summary 8.11 Summary 8-14 A Z1 R
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Precision 9.2 Precision 9-2 The lon
Page 118 and 119: Bandwidth 9-4 A aR G R F R G (9-2
Page 120 and 121: Stability 9.4 Stability 9-6 Substit
Page 122 and 123: Equation Comparison 9-8 R G = 100
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Page 126 and 127: Characterization 10-2 Noise Signal
Page 128 and 129: Types of Noise 10.2.5 Noise Units 1
Page 130 and 131: Types of Noise 10-6 Shot noise is
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Page 134 and 135: Noise Colors Figure 10-4. Avalanche
Page 136 and 137: Op Amp Noise 10.4.3 Red/Brown Noise
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Page 140 and 141: Op Amp Noise 10.5.4 Inverting Op Am
Page 142 and 143: Op Amp Noise 10.5.6 Differential Op
Page 144 and 145: Putting It All Together 10-20 Vn Vn
Page 146 and 147: Putting It All Together 10-22 volta
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Page 150 and 151: Operational Amplifier Parameter Glo
Page 156 and 157: Additional Parameter Information 11
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Page 176 and 177: 12.2 Transducer Types 12-6 This is
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Page 186 and 187: Table 12-3. Op Amp Selection 12-16
Page 188 and 189: 12-18 this yields m = 16.16. The re
Page 190 and 191: 12-20 0.97R 1 VREF(MIN) VREF 50 m
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Page 196 and 197: Wireless Systems 13-2 Signal @ - 10
Page 198 and 199: Wireless Systems 13-4 900 MHz Figur
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Page 202 and 203: Selection of ADCs/DACs 13-8 Therefo
Page 204 and 205: Factors Influencing the Choice of O
Page 206 and 207: Anti-Aliasing Filters 13-12 anti-al
Page 208 and 209: Communication D/A Converter Reconst
Page 210 and 211: External Vref Circuits for ADCs/DAC
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Page 216 and 217: References 13.9 References 13-22 [1
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Understanding the D/A Converter and
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Understanding the D/A Converter and
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D/A Converter Error Budget 14-6 rat
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D/A Converter Error Budget 14-8 The
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D/A Converter Errors and Parameters
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Compensating For DAC Capacitance 14
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Increasing Op Amp Buffer Amplifier
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Increasing Op Amp Buffer Amplifier
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14-24
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Requirements for Oscillation 15-2 u
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Gain in the Oscillator 15-4 The fre
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Active Element (Op Amp) Impact on t
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Analysis of the Oscillator Operatio
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Sine Wave Oscillator Circuits 15-10
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References 15.8 References 15-22 [1
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Fundamentals of Low-Pass Filters 16
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Low-Pass Filter Design 16-12 1st or
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Low-Pass Filter Design Example 16-1
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Low-Pass Filter Design 16-16 In ord
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Low-Pass Filter Design 16.3.2.2 Mul
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Low-Pass Filter Design Second Filte
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High-Pass Filter Design 16-22 |A|
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High-Pass Filter Design 16-24 To di
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High-Pass Filter Design 16-26 Throu
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Band-Pass Filter Design 16-28 |A| [
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Band-Pass Filter Design 16-30 The g
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Band-Pass Filter Design 16-32 out a
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Band-Pass Filter Design 16-34 After
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Band-Rejection Filter Design 16-36
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All-Pass Filter Design 16-42 2 i
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All-Pass Filter Design 16.7.1 First
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All-Pass Filter Design 16-46 V IN f
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Practical Design Hints 16-48 low-pa
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Practical Design Hints V IN 16-50 C
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Practical Design Hints 16-52 If thi
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Practical Design Hints 16-54 f T 1
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Filter Coefficient Tables Table 16-
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16-64
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General Considerations 17.1.3 Noise
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PCB Mechanical Construction 17-4 Te
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PCB Mechanical Construction 17.2.2.
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Grounding 17-8 DIGITAL + DIGITAL -
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Grounding 17-10 CONNECTOR POWER SUP
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The Frequency Characteristics of Pa
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Decoupling 17-20 For example, a 0.4
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Decoupling 17-22 EQUIVALENT SERIES
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Packages 17.7 Packages 17-24 N1 IN-
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Packages 17-26 IN1 + OUT1 IN2 IN3 O
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Summary 17-28 HALF SUPPLY GOOD _ +
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17-30
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Introduction 18-2 swing at V CC = 5
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Dynamic Range 18-4 VIN VnR Figure 1
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Input Common-Mode Range 18-6 sible
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Input Common-Mode Range 18-8 VCC GN
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Input Common-Mode Range 18-10 V µ
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Shutdown and Low Current Drain 18-1
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Transducer to ADC Analog Interface
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DAC to Actuator Analog Interface 18
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DAC to Actuator Analog Interface 18
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Comparison of Op Amps 18-20 When DA
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Summary 18.11 Summary 18-22 Always
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"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

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