20.07.2013 Views

"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

"Chapter 1 - The Op Amp's Place in the World" - HTL Wien 10

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Additional Parameter Information<br />

11.3.2 Input Current<br />

11-<strong>10</strong><br />

<strong>The</strong> <strong>in</strong>put circuitry of all op amps requires a certa<strong>in</strong> amount of bias current for proper operation.<br />

<strong>The</strong> <strong>in</strong>put bias current, I IB, is computed as <strong>the</strong> average of <strong>the</strong> two <strong>in</strong>puts:<br />

I IB I N I P <br />

2<br />

(11–1)<br />

CMOS and JFET <strong>in</strong>puts offer much lower <strong>in</strong>put current than standard bipolar <strong>in</strong>puts. Figure<br />

11–3 shows a typical test circuit for measur<strong>in</strong>g <strong>in</strong>put bias currents.<br />

<strong>The</strong> difference between <strong>the</strong> bias currents at <strong>the</strong> <strong>in</strong>vert<strong>in</strong>g and non<strong>in</strong>vert<strong>in</strong>g <strong>in</strong>puts is called<br />

<strong>the</strong> <strong>in</strong>put offset current, I IO = I N–I P. Offset current is typically an order of magnitude less<br />

than bias current.<br />

Vref<br />

Figure 11–3.Test Circuit – I IB<br />

S2<br />

IN<br />

<strong>10</strong> MΩ<br />

_<br />

DUT<br />

+<br />

Vout<br />

1 nF<br />

<strong>10</strong> MΩ<br />

IP<br />

1 nF<br />

S1<br />

S1 Closed<br />

IP <br />

Vout Vref<br />

<strong>10</strong>7 S2 Closed<br />

IN <br />

Vout Vref<br />

<strong>10</strong>7 Input bias current is of concern when <strong>the</strong> source impedance is high. If <strong>the</strong> op amp has high<br />

<strong>in</strong>put bias current, it will load <strong>the</strong> source and a lower than expected voltage is seen. <strong>The</strong><br />

best solution is to use an op amp with ei<strong>the</strong>r CMOS or JFET <strong>in</strong>put. <strong>The</strong> source impedance<br />

can also be lowered by us<strong>in</strong>g a buffer stage to drive <strong>the</strong> op amp that has high <strong>in</strong>put bias<br />

current.<br />

In <strong>the</strong> case of bipolar <strong>in</strong>puts, offset current can be nullified by match<strong>in</strong>g <strong>the</strong> impedance<br />

seen at <strong>the</strong> <strong>in</strong>puts. In <strong>the</strong> case of CMOS or JFET <strong>in</strong>puts, <strong>the</strong> offset current is usually not<br />

an issue and match<strong>in</strong>g <strong>the</strong> impedance is not necessary.<br />

<strong>The</strong> average temperature coefficient of <strong>in</strong>put offset current, αI IO, specifies <strong>the</strong> expected<br />

<strong>in</strong>put offset drift over temperature. Its units are µA/°C. I IO is measured at <strong>the</strong> temperature<br />

extremes of <strong>the</strong> part, and αI IO is computed as ∆I IO/∆C.

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!