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A<br />
B<br />
C<br />
D<br />
TS5, <strong>BCT</strong>-<strong>1510</strong>, <strong>BCT</strong>-<strong>1520</strong>,<br />
<strong>BCT</strong>-<strong>1530</strong><br />
3.3 MAIN ASSY (2/7)<br />
12<br />
A<br />
1 2 3 4<br />
A 2/7 MAIN ASSY (2/7)<br />
DMXCPU BLOCK<br />
(TS5 : BWE1103)<br />
(<strong>BCT</strong>-<strong>1510</strong> : BWE1115)<br />
(<strong>BCT</strong>-<strong>1520</strong> : BWE1115)<br />
(<strong>BCT</strong>-<strong>1530</strong> : BWE1110)<br />
A 3/7<br />
A 3/7<br />
2/7<br />
A 7/7<br />
A 6/7<br />
A 7/7<br />
A 7/7<br />
A 1/7<br />
A 5/7<br />
A 7/7<br />
A 3/7<br />
1 2 3 4<br />
A 7/7<br />
IC2001<br />
A 7/7<br />
A 7/7<br />
TS5/<strong>BCT</strong>-<strong>1510</strong>/<strong>BCT</strong>-<strong>1520</strong> : STI5512AWE<br />
<strong>BCT</strong>-<strong>1530</strong> : STI5512AWE/E<br />
Programmable Transport IC<br />
A 7/7<br />
A 1
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