JAEA-Review-2010-065.pdf:15.99MB - 日本原子力研究開発機構

Feasibility Study on a 90 nm Bulk CMOS Process for
Applicability to Space Environments
A. Maru a) , H. Shindou a) , S. Kuboyama a) , T. Hirao b) and T. Ohshima b)
a) Aerospace Research and Development Directorate, Japan Aerospace Exploration Agency (JAXA),
b) Environment and Industrial Materials Research Division, QuBS, JAEA
Recently, due to the requirements for higher density
integration and device scaling, the logical circuits have been
designed with < 100 nm design rule. Single-Event Upset
(SEU) and Single-Event Transient (SET) phenomena are
serious problems for those integrated circuits, because their
supply voltage and the threshold to the phenomena are also
decreasing. It is said that DICE (Dual Interlocked Storage
Cell) circuit is the hardened topology against SEU 1, 2) . The
DICE circuit keeps data using two memory nodes, and if
data inversion has occurred by incident particles on the one
hand memory node, the correct data is rewritten by the other
hand memory node. Therefore, DICE circuit has excellent
radiation tolerance. However, in the highly integrated
circuits, it is occurred that two neighboring transistors are
simultaneously inverted by an incident particle due to the
charge sharing mechanism. Therefore, it is important for
the design of those circuits to estimate the extent of the
charge sharing.
In this feasibility study, the applicability to space
environments of a 90 nm bulk CMOS process was evaluated
by heavy ions and the SEU cross section was calculated.
For detailed evaluation, we also performed the angled
irradiation. The experimental results suggested there are
the critical angles in the DICE memory circuit.
At first, we evaluated the effectiveness of RHBD
apploarch for 90 nm CMOS process, by using the heavy
ions delivered from the AVF cyclotron at JAEA. As
shown in Fig. 1, the latch cell with RHBD methodology for
90 nm, the DICE topology, has excellent radiation hardness.
However, it is said that if two critical off state transistors
Cross Section [cm 2 /bit]
1-04
1.E-07
1.E-08
1.E-09
Standard LAT
DICE LAT
0 20 40 60 80 100
LET [MeV/(mg/cm 2 )]
Fig. 1 SEU cross-sections as a function of Linear
energy transfer for Standard and DICE latch circuits.
JAEA-Review 2010-065
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in the DICE circuit upset simultaneously, the memorized
data in the DICE memory is lost. Therefore we performed
the angled irradiation for DICE memory circuit and the SEU
cross section against incident angle was calculated.
Figure 2 shows SEU cross-sections as a function of
incident angle when Kr (LET= 40.3 MeV/mg/cm 2 ) particles
were irradiated. In our DICE circuit, the most critical
angle is estimated to be 52 degree. So, if the irradiated
heavy ion incidents from that angle, the particle pass
through the two critical transistors in the DICE circuit.
Therefore, although it is considered that the actual distance
of the two adjacent transistors in the off state to hold the
logic state is one of the critical parameters to prevent SEUs,
in addition to this parameter, some artifice to prevent SEUs
by the angled irradiation is necessary. In future work, we
plan to design the circuit that optimized the actual layout
and added the countermeasure against the angled irradiation
in order to achieve SEU immunity up to 64 MeV/(mg/cm 2 )
of LET.
References
1) M.P.Baze, et al., EEE Trans. Nucl. Sci., Vol. 55 (2008)
3295.
2) Kuande Wang, et al., Canadian Conference on Electrical
and Computer Engineering, (2009) 1076.
Fig. 2 SEU cross-sections against incident angle.