Accurate HFSS Simulation of SMT Components in Sip and MCM ...
Accurate HFSS Simulation of SMT Components in Sip and MCM ...
Accurate HFSS Simulation of SMT Components in Sip and MCM ...
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Weim<strong>in</strong> Sun <strong>and</strong> Hongxiao Shao<br />
Skyworks Solutions<br />
16 Oct 2007<br />
<strong>Accurate</strong> <strong>HFSS</strong> <strong>Simulation</strong> <strong>of</strong> <strong>SMT</strong><br />
<strong>Components</strong> <strong>in</strong> SiP <strong>and</strong> <strong>MCM</strong> Designs
Outl<strong>in</strong>e<br />
2 10/16/2007<br />
• Wireless Market Evolution<br />
• Why <strong>SMT</strong> <strong>Components</strong>?<br />
• A Sample <strong>MCM</strong> Lam<strong>in</strong>ate Design<br />
• <strong>HFSS</strong> <strong>Simulation</strong> Setups for a SMD<br />
• Intr<strong>in</strong>sic Inductance <strong>of</strong> Lumped Port<br />
• How to Split a Port with No GND Reference<br />
• Recommendations
Mobile H<strong>and</strong>set Evolution<br />
3 10/16/2007
Mobile H<strong>and</strong>set Market Cont<strong>in</strong>ues to Grow<br />
4 10/16/2007<br />
Market Forecast by Air Interface
H<strong>and</strong>set’s Eng<strong>in</strong>e Is a <strong>MCM</strong>/PCB<br />
5 10/16/2007<br />
Baseb<strong>and</strong><br />
Mixed Signal<br />
Power Management<br />
Power Amplifier<br />
Switch/Filter
Skyworks Is A Leader <strong>in</strong> PA / Front-End Module<br />
6 10/16/2007
SMD Widely Used <strong>in</strong> <strong>MCM</strong>/FEMs<br />
7 10/16/2007<br />
SMDs<br />
<strong>MCM</strong>
What Challenges <strong>in</strong> H<strong>and</strong>set RF Design?<br />
8 10/16/2007<br />
• Integration <strong>of</strong> Multi-Medium St<strong>and</strong>ards<br />
WLAN, GPRS, WCDMA, GPS, MP3, Video, Web…<br />
• System M<strong>in</strong>iaturization<br />
• Lower Cost<br />
SOC, SiP, <strong>MCM</strong>, Stacked Die …<br />
Lam<strong>in</strong>ate PCB, <strong>SMT</strong> <strong>Components</strong>, Shrunk Die, Larger Wafer…<br />
• Improved Performance<br />
Efficiency, Power, Noise/Xtalk, EMI, Z Match<strong>in</strong>g …<br />
• System <strong>and</strong> Module Level A/D Mixed <strong>Simulation</strong>/Design<br />
EM Sim, Fast Spice, Mixed Signal Sim …
How EM <strong>Simulation</strong> Helps RF Design?<br />
9 10/16/2007<br />
• Increased Dem<strong>and</strong> for EM Co-simulation<br />
IR Drop, Xtalk, EMI, Embedded Match<strong>in</strong>g …<br />
• Passive Design Optimization<br />
Inductor, T-l<strong>in</strong>e, Wire-Bond Tun<strong>in</strong>g, Vias …<br />
• 3D Module Design<br />
SMD, Stacked Die, Package, Wires, Module …<br />
• Distributed Circuit at High Frequency<br />
Beyond Limit <strong>of</strong> Lumped RLC, SPICE, Quasi-static Solution…<br />
• True Full-Wave Solution<br />
Loss, Coupl<strong>in</strong>g, Dispersion, Radiation, Cross-talk …
Why Use <strong>SMT</strong> <strong>Components</strong>?<br />
• Achieve Large L/C Value <strong>of</strong>f-Chip<br />
• Higher Q (lower loss)<br />
• Easy Tun<strong>in</strong>g/Design Optimization<br />
• Reduced Development Cycle Time<br />
• ‘Lumped’ <strong>and</strong> ‘Discrete’ for <strong>Simulation</strong><br />
• Competitive Vendors –> Low cost<br />
10 10/16/2007<br />
SMD<br />
PA<br />
<strong>MCM</strong>
A Sample EM <strong>Simulation</strong> Flow<br />
11 10/16/2007<br />
APD Ans<strong>of</strong>tl<strong>in</strong>k 3D Model<br />
S11/S21<br />
5<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
-50<br />
SMD<br />
-55<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)<br />
<strong>MCM</strong>/Board Data<br />
SnP/Spice Model
SMD <strong>Simulation</strong> Facilities <strong>in</strong> <strong>HFSS</strong><br />
• Add Physical SMD <strong>in</strong>to Model<br />
•Treat SMD as Part <strong>of</strong> the Layout Design<br />
•Direct FEM Mesh<strong>in</strong>g on F<strong>in</strong>e Structure <strong>of</strong> the SMD<br />
• Assign Surface/Boundary with Lumped SMD Parasitic<br />
•Introduce an Artificial Impedance Surface near SMD<br />
•Make the Z-Surface Equivalent to SMD Parasitic from Vendor<br />
• Def<strong>in</strong>e a Lumped Port <strong>and</strong> Simulate <strong>in</strong> SPICE<br />
•Def<strong>in</strong>e Lumped Port at SMD Pads<br />
•Create S-Parameter Model <strong>in</strong>clud<strong>in</strong>g SMD ports<br />
•Spice <strong>Simulation</strong> <strong>of</strong> the Design with the S-Parameter Model<br />
12 10/16/2007
SMD Model<strong>in</strong>g <strong>in</strong> <strong>HFSS</strong><br />
– Physical SMD Model<br />
13 10/16/2007<br />
•<strong>Accurate</strong> <strong>and</strong> Physical<br />
•But Most SMD Internal Material/Geometry Data Not Available<br />
•Need F<strong>in</strong>e Mesh to Account for Micro-Structure Details<br />
•CPU/Memory Expensive<br />
•Not Practical <strong>in</strong> Design Optimization/Tun<strong>in</strong>g
SMD Model<strong>in</strong>g <strong>in</strong> <strong>HFSS</strong><br />
– Lumped Port vs. Lumped RLC Surface<br />
Lumped Surface (RLC)<br />
• SMD <strong>in</strong>cluded <strong>in</strong> the model<br />
• SMD bulk dielectric effect<br />
• Fewer ports <strong>and</strong> smaller S-parameter file<br />
14 10/16/2007<br />
Lumped Port<br />
• Larger S-parameter file/matrix<br />
• Easy SMD tun<strong>in</strong>g/design optimization<br />
• May need to calibrate out SMD bulk dielectric
Setup for A Lumped SMD Port<br />
S<strong>in</strong>gle Port<br />
15 10/16/2007<br />
Port 1<br />
…..<br />
Port 1<br />
Port 2<br />
…..<br />
Dual Ports PEC to Ground Ports
A <strong>MCM</strong> Lam<strong>in</strong>ate Design<br />
16 10/16/2007<br />
Lam<strong>in</strong>ate Design 3D Model<br />
Selected Nets <strong>in</strong>to a 3D Model<br />
Probed
A <strong>MCM</strong> Lam<strong>in</strong>ate Design<br />
-- Equivalent Net Circuit Modeled<br />
Vcc RF_out<br />
17 10/16/2007<br />
<strong>SMT</strong> <strong>Components</strong><br />
L<br />
L1<br />
R=<br />
L<br />
L3<br />
L<br />
L2<br />
R=<br />
R<br />
C<br />
Port1 R1<br />
C3<br />
Port2<br />
C<br />
C_Vcc_shunt<br />
C<br />
C5<br />
Term<br />
Term7<br />
Num=7<br />
Z=50 Ohm<br />
Port1<br />
Port2<br />
Term S5P<br />
Term8 SNP4<br />
Num=8<br />
Z=50 Ohm<br />
1<br />
5<br />
2<br />
Vcc_port<br />
4<br />
3<br />
Ref<br />
R<br />
R5<br />
C3_port<br />
C5_port<br />
L<br />
L13<br />
L<br />
L5<br />
R=<br />
L<br />
L4<br />
C<br />
C_3<br />
C<br />
C14<br />
C<br />
C_5
SMD Model<strong>in</strong>g <strong>in</strong> <strong>HFSS</strong><br />
– Lumped Port vs. Lumped RLC Surface<br />
18 10/16/2007<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
P<strong>in</strong>k: S<strong>in</strong>gle-Ended SMD Port Used<br />
Brown: Dual SMD Ports Used<br />
Green: SMD Modeled with Lumped RLC<br />
Why ??<br />
-50<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)
S<strong>in</strong>gle SMD Port vs. Dual SMD Ports<br />
19 10/16/2007<br />
L<br />
L1<br />
R<br />
R1<br />
C<br />
C1<br />
Port 1<br />
…..<br />
SMD<br />
SMD C<br />
Forced GND on schematic<br />
• Mathematically Equivalent<br />
S Matrix – Mapp<strong>in</strong>g ∆V <strong>of</strong> SMD Ends<br />
• Physically SMD End not GNDed<br />
• Easy to Def<strong>in</strong>e Port for SMDs<br />
L<br />
L1<br />
R<br />
R1<br />
C1<br />
Port 1<br />
Port 2<br />
…..<br />
• Schematic <strong>and</strong> Physical Connection Matched<br />
• Bias <strong>and</strong> Decoup SMDs Can be Modeled<br />
• But Difficult to Def<strong>in</strong>e Ports Ref to GND
Post Port Split from S/Y Matrix<br />
20 10/16/2007<br />
Port 1<br />
I 1<br />
S<br />
I 2<br />
V 1 V 2<br />
S to Y<br />
⎡Y<br />
⎢<br />
⎣Y<br />
1+1 Port 2+1 Port<br />
11<br />
21<br />
Y<br />
Y<br />
12<br />
22<br />
⎤<br />
⎥<br />
⎦<br />
Port 2<br />
Port 1<br />
Port 2<br />
V 1<br />
V 2<br />
I 1<br />
I 2<br />
S<br />
I 3<br />
V 3<br />
Force: I 1 = - I 2 = I 1<br />
V 1 = - V 2 = 0.5 V 1<br />
⎡2Y<br />
⎢<br />
⎢<br />
0<br />
⎢⎣<br />
Y<br />
11<br />
21<br />
0<br />
2Y<br />
−Y<br />
11<br />
21<br />
Y to S<br />
Y<br />
12<br />
−Y<br />
Y<br />
22<br />
Port 3<br />
12<br />
⎤<br />
⎥<br />
⎥<br />
⎥⎦
21 10/16/2007<br />
Post Port Split from S/Y Matrix<br />
-- General N Port Matrix<br />
NxN Matrix with the i th Port Split <strong>in</strong>to Dual Ports (i th <strong>and</strong> (i+1) th )<br />
NxN<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎦<br />
⎤<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎣<br />
⎡<br />
N<br />
N<br />
N<br />
N<br />
N<br />
N<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
,<br />
2<br />
,<br />
1<br />
,<br />
,<br />
2<br />
2<br />
,<br />
2<br />
1<br />
,<br />
2<br />
,<br />
1<br />
2<br />
,<br />
1<br />
1<br />
,<br />
1<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
1)<br />
1)x(N<br />
(N +<br />
+<br />
+<br />
−<br />
+<br />
+<br />
+<br />
+<br />
+<br />
−<br />
+<br />
+<br />
+<br />
−<br />
+<br />
−<br />
−<br />
+<br />
−<br />
−<br />
−<br />
−<br />
−<br />
−<br />
+<br />
−<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎥<br />
⎦<br />
⎤<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎢<br />
⎣<br />
⎡<br />
−<br />
−<br />
−<br />
−<br />
−<br />
−<br />
−<br />
−<br />
N<br />
N<br />
i<br />
N<br />
i<br />
N<br />
i<br />
N<br />
i<br />
N<br />
N<br />
N<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
N<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
N<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
N<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
i<br />
N<br />
i<br />
i<br />
i<br />
i<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
Y<br />
,<br />
1<br />
,<br />
,<br />
,<br />
1<br />
,<br />
1<br />
,<br />
,<br />
1<br />
1<br />
,<br />
1<br />
,<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
,<br />
1<br />
,<br />
,<br />
1<br />
,<br />
1<br />
,<br />
,<br />
1<br />
,<br />
,<br />
1<br />
,<br />
1<br />
,<br />
,<br />
1<br />
1<br />
.<br />
1<br />
,<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
,<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
1<br />
,<br />
1<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
2<br />
0<br />
...<br />
...<br />
0<br />
2<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
...<br />
i i+1 N+1<br />
i<br />
i+1
Post Port Split<br />
22 10/16/2007<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
P<strong>in</strong>k: S<strong>in</strong>gle-Ended SMD Port Used<br />
Brown: Dual SMD Ports Used<br />
Green: S<strong>in</strong>gle SMD Port with Post Split <strong>in</strong>to Two<br />
-50<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)
<strong>Simulation</strong> vs. Measurement<br />
23 10/16/2007<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
Term<br />
Term7<br />
Num=7<br />
Z=50 Ohm<br />
Port1<br />
Port2<br />
Term S5P<br />
Term8 SNP4<br />
Num=8<br />
Z=50 Ohm<br />
1<br />
5<br />
2<br />
Vcc_port<br />
4<br />
3<br />
Ref<br />
C3_port<br />
C5_port<br />
Measurement<br />
L<br />
L13<br />
L=0.25 nH<br />
R=0.2<br />
L<br />
L4<br />
L=0.25 nH<br />
R=0.2<br />
C<br />
C_3<br />
C<br />
C_5<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)<br />
R<br />
R5<br />
L<br />
L5<br />
R=<br />
??<br />
C<br />
C14<br />
Full SMD Parasitic Used <strong>in</strong> Schematic<br />
Notch sensitive to L13 !!
Any Intr<strong>in</strong>sic Inductance <strong>in</strong> a Lumped Port ?<br />
24 10/16/2007<br />
W<br />
Current Sheet<br />
l<br />
∫ • ∝ AdV J L<br />
µ 0l<br />
⎡ 2l<br />
W ⎤<br />
L =<br />
⎢<br />
ln( ) + 0.<br />
50049 +<br />
2π<br />
⎥<br />
⎣ W<br />
3l<br />
⎦
Intr<strong>in</strong>sic Inductance <strong>in</strong> a Lumped Port<br />
25 10/16/2007<br />
Term<br />
Term7<br />
Num=7<br />
Z=50 Ohm<br />
Port1<br />
Port2<br />
Term S5P<br />
Term8 SNP4<br />
Num=8<br />
Z=50 Ohm<br />
Vcc_port<br />
R<br />
R5<br />
C3_port<br />
C5_port<br />
Port Intr<strong>in</strong>sic Inductance<br />
Corrected<br />
1<br />
5<br />
2<br />
4<br />
3<br />
Ref<br />
L<br />
L5<br />
R=<br />
L<br />
L13<br />
L=0.06 nH<br />
L<br />
L4<br />
L=0.06 nH<br />
S21/S11 (dB)<br />
C<br />
C_3<br />
C<br />
C14<br />
C<br />
C_5<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
Brown: SMD Parasitic from Data Sheet<br />
Blue: Measurement<br />
P<strong>in</strong>k: SMD Port Intr<strong>in</strong>sic L Deducted<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)
Intr<strong>in</strong>sic Inductance vs. Port Shape<br />
26 10/16/2007<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)<br />
Slim port<br />
Wide port<br />
50pH difference to shift the Notch
A Second Check with Measurement<br />
27 10/16/2007<br />
•S21 Matches Well<br />
•S11/S22 Show Different Circle Diameter on Smith Chart<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHZ)<br />
S21<br />
S11<br />
P<strong>in</strong>k: <strong>HFSS</strong> Blue: Measurement<br />
S11/S22<br />
freq (100.0MHz to 6.000GHz)<br />
S22
<strong>Simulation</strong> or Measurement?<br />
-- A Second Try With an FDTD Simulator<br />
28 10/16/2007<br />
•<strong>HFSS</strong> <strong>and</strong> FDTD Match Well (S21, S11, S22)<br />
•Still S11/S22 Not Match to Measurement<br />
S21/S11 (dB)<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)<br />
S21<br />
S11<br />
P<strong>in</strong>k: <strong>HFSS</strong> Blue: Measurement Green: FDTD<br />
S11/S22<br />
freq (100.0MHz to 6.000GHz)
Is Reference 50 Ohm at Probed Port?<br />
29 10/16/2007<br />
Probed Spot<br />
50Ω<br />
?? Ω<br />
Model<br />
Jsuf<br />
@1.5 GHz<br />
Port
Is Reference 44 Ohm at Probed Port?<br />
S21/S11 (dB)<br />
30 10/16/2007<br />
0<br />
-5<br />
-10<br />
-15<br />
-20<br />
-25<br />
-30<br />
-35<br />
-40<br />
Term<br />
Term3<br />
Num=3<br />
Z=44 Ohm<br />
Measurement Data<br />
1<br />
Ref<br />
S2P<br />
SNP1<br />
If reference to 44 Ohm (measured)<br />
-45<br />
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0<br />
Freq (GHz)<br />
P<strong>in</strong>k: <strong>HFSS</strong> Blue: Measurement Green: FDTD<br />
2<br />
S11/S22<br />
Term<br />
Term4<br />
Num=4<br />
Z=50 Ohm<br />
freq (100.0MHz to 6.000GHz)
Summary<br />
31 10/16/2007<br />
• Use <strong>of</strong> SMDs is Very Popular <strong>in</strong> <strong>MCM</strong>/SiP RFIC Designs<br />
• SMD Can Be Modeled <strong>and</strong> Simulated Well with <strong>HFSS</strong> <strong>and</strong> Spice<br />
• Lumped SMD Port Seems Preferable over Lumped RLC<br />
• Lumped SMD Port Bears Intr<strong>in</strong>sic Inductance, <strong>and</strong><br />
Port Aspect Ratio Could Make Difference<br />
• S<strong>in</strong>gle-Ended Port with Post Split Can Model SMD Equally Well
Recommendations<br />
• Facilitate Lumped Serial RLC Boundary<br />
• Implement Post Port Split Matrix Operation<br />
• Explore Difference between Lumped Boundary vs. Lumped Port<br />
• Facilitate Voltage Contour <strong>in</strong> Fields Plot<br />
• Option to Deembed Lumped Port Intr<strong>in</strong>sic Inductance<br />
–- Name as SMD Port?<br />
32 10/16/2007
Acknowledgement<br />
33 10/16/2007<br />
• Special Thanks to Russ Reisner from Skyworks Solutions<br />
for Shar<strong>in</strong>g the Measurement Data <strong>and</strong> Explor<strong>in</strong>g the<br />
Sample Lam<strong>in</strong>ate Design
34 10/16/2007