Xilinx Synthesis Technology User Guide

neither Full nor Parallel
module notfull_notparallel
(sel1, sel2, i1, i2, o1);
input [1:0] sel1, sel2;
input [1:0] i1, i2;
output [1:0] o1;
reg [1:0] o1;
always @(sel1 or sel2)
begin
case (2'b00)
sel1: o1 = i1;
sel2: o1 = i2;
endcase
end
endmodule
HDL Coding Techniques
XST automatically determines the characteristics of the Case
statements and generates logic using multiplexers, priority encoders
and latches that best implement the exact behavior of the Case
statement.
This characterization of the Case statements can be guided or
modified by using the Case Implementation Style parameter. Please
refer to the “Design Constraints” chapter for more details. Accepted
values for this parameter are default, full, parallel and
full-parallel.
• If the default is used, XST will implement the exact behavior of
the Case statements.
• If full is used, XST will consider that Case statements are
complete and will avoid latch creation.
• If parallel is used, XST will consider that the branches cannot
occur in parallel and will not use a priority encoder.
• If full-parallel is used, XST will consider that Case statements are
complete and that the branches cannot occur in parallel, therefore
saving latches and priority encoders.
XST User Guide 2-75