Xilinx Synthesis Technology User Guide

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
HDL Coding Techniques
entity shiftregluts is
port(CLK : in std_logic;
DATA : in std_logic;
CE : in std_logic;
A : in std_logic_vector(3 downto 0);
Q : out std_logic);
end shiftregluts;
architecture rtl of shiftregluts is
constant DEPTH_WIDTH : integer := 16;
type SRL_ARRAY is array (0 to DEPTH_WIDTH-1) of
std_logic;
-- The type SRL_ARRAY can be array
-- (0 to DEPTH_WIDTH-1) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- or array (DEPTH_WIDTH-1 downto 0) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- (the subtype is forward (see below))
signal SRL_SIG : SRL_ARRAY;
begin
PROC_SRL16 : process (CLK)
begin
if (CLK'event and CLK = '1') then
if (CE = '1') then
SRL_SIG