Xilinx Synthesis Technology User Guide

Dynamic Shift Register
module shift (C, SI, LEFT_RIGHT, PO);
input C,SI,LEFT_RIGHT;
output PO;
reg [7:0] tmp;
always @(posedge C)
begin
if (LEFT_RIGHT==1'b0)
begin
tmp = {tmp[6:0], SI};
end
else
begin
tmp = {SI, tmp[6:0]};
end
end
assign PO = tmp;
endmodule
HDL Coding Techniques
XST can infer Dynamic shift registers. Once a dynamic shift register
has been identified, its characteristics are handed to the XST macro
generator for optimal implementation using SRL16x primitives
available in Virtex or SRL16Cx in Virtex-II and Virtex-II Pro.
16-bit Dynamic Shift Register with Positive-Edge
Clock, Serial In and Serial Out
The following table shows pin definitions for a dynamic register. The
register can be either serial or parallel; be left, right or parallel; have a
synchronous or asynchronous clear; and have a width up to 16 bits.
IO Pins Description
Clk Positive-Edge Clock
SI Serial In
AClr Asynchronous Clear (optional)
SClr Synchronous Clear (optional)
SLoad Synchronous Parallel Load (optional)
XST User Guide 2-69