Xilinx Synthesis Technology User Guide

Verilog Code
HDL Coding Techniques
Following is the Verilog code for an 8-bit shift-left register with a
positive-edge clock, asynchronous parallel load, serial in, and serial
out.
module shift (C, ALOAD, SI, D, SO);
input C,SI,ALOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
tmp = D;
else
begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
8-bit Shift-Left Register with Positive-Edge Clock,
Synchronous Parallel Load, Serial In, and Serial Out
Note For this example XST will not infer SRL16.
The following table shows pin definitions for an 8-bit shift-left
register with a positive-edge clock, synchronous parallel load, serial
in, and serial out.
IO Pins Description
C Positive-Edge Clock
SI Serial In
SLOAD Synchronous Parallel Load (active High)
D[7:0] Data Input
SO Serial Output
XST User Guide 2-65