Xilinx Synthesis Technology User Guide

XST User Guide
Shift Registers
Verilog Code
Following is the Verilog code for a 4-bit unsigned up accumulator
with asynchronous clear.
module accum (C, CLR, D, Q);
input C, CLR;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
tmp = tmp + D;
end
assign Q = tmp;
endmodule
No constraints are available.
In general a shift register is characterized by the following control
and data signals, which are fully recognized by XST:
• clock
• serial input
• asynchronous set/reset
• synchronous set/reset
• synchronous/asynchronous parallel load
• clock enable
• serial or parallel output. The shift register output mode may be:
♦ serial: only the contents of the last flip-flop are accessed by
the rest of the circuit
♦ parallel: the contents of one or several flip-flops, other than
the last one, are accessed
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