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Xilinx Synthesis Technology User Guide

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XST <strong>User</strong> <strong>Guide</strong><br />

Verilog Code<br />

Following is the Verilog code for a 4-bit unsigned down counter with<br />

synchronous set.<br />

module counter (C, S, Q);<br />

input C, S;<br />

output [3:0] Q;<br />

reg [3:0] tmp;<br />

always @(posedge C)<br />

begin<br />

if (S)<br />

tmp = 4'b1111;<br />

else<br />

tmp = tmp - 1'b1;<br />

end<br />

assign Q = tmp;<br />

endmodule<br />

4-bit Unsigned Up Counter with Asynchronous Load<br />

from Primary Input<br />

The following table shows pin definitions for a 4-bit unsigned up<br />

counter with asynchronous load from primary input.<br />

IO Pins Description<br />

C Positive-Edge Clock<br />

ALOAD Asynchronous Load (active High)<br />

D[3:0] Data Input<br />

Q[3:0] Data Output<br />

VHDL Code<br />

Following is the VHDL code for a 4-bit unsigned up counter with<br />

asynchronous load from primary input.<br />

library ieee;<br />

use ieee.std_logic_1164.all;<br />

use ieee.std_logic_unsigned.all;<br />

2-40 <strong>Xilinx</strong> Development System

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