Xilinx Synthesis Technology User Guide

XST User Guide
Description Using Concurrent Assignment
In the following two examples, note that comparing to 0 instead of 1
will infer the BUFT primitive instead of the BUFE macro. (The BUFE
macro has an inverter on the E pin.)
VHDL Code
Following is VHDL code for a tristate element using a concurrent
assignment.
library ieee;
use ieee.std_logic_1164.all;
entity three_st is
port(T : in std_logic;
I: in std_logic;
O: out std_logic);
end three_st;
architecture archi of three_st is
begin
O