Xilinx Synthesis Technology User Guide

HDL Coding Techniques
Verilog Code
Following is the equivalent Verilog code for a latch with a positive
gate.
module latch (G, D, Q);
input G, D;
output Q;
reg Q;
always @(G or D)
begin
if (G)
Q = D;
end
endmodule
Latch with Positive Gate and Asynchronous Clear
The following figure shows a latch with positive gate and
asynchronous clear.
D
G
CLR
LDC
X4070
Q
The following table shows pin definitions for a latch with positive
gate and asynchronous clear.
IO Pins Description
D Data Input
G Positive Gate
CLR Asynchronous Clear (active High)
Q Data Output
XST User Guide 2-27