Xilinx Synthesis Technology User Guide

XST User Guide
Verilog Code
Following is the equivalent Verilog code for the flip-flop with a
positive-edge clock and clock enable.
module flop (C, D, CE, Q);
input C, D, CE;
output Q;
reg Q;
always @(posedge C)
begin
if (CE)
Q = D;
end
endmodule
4-bit Register with Positive-Edge Clock,
Asynchronous Set and Clock Enable
The following figure shows a 4-bit register with positive-edge clock,
asynchronous set and clock enable.
PRE
D
CE
C
FDPE
Q
X3721
The following table shows pin definitions for a 4-bit register with
positive-edge clock, asynchronous set and clock enable.
IO Pins Description
D[3:0] Data Input
C Positive-Edge Clock
PRE Asynchronous Set (active High)
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