Xilinx Synthesis Technology User Guide

HDL Coding Techniques
The following table shows pin definitions for a flip-flop with positive
edge clock and clock enable.
IO Pins Description
D Data Input
C Positive-Edge Clock
CE Clock Enable (active High)
Q Data Output
VHDL Code
Following is the equivalent VHDL code for the flip-flop with a
positive-edge clock and clock Enable.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D, CE : in std_logic;
Q : out std_logic);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C'event and C='1') then
if (CE='1') then
Q