Xilinx Synthesis Technology User Guide

XST User Guide
# OR2 : 36
# XOR2 : 9
# FlipFlops/Latches : 11
# FDCE : 8
# FTC : 3
# IO Buffers : 27
# IBUF : 3
# OBUF : 24
# Others : 1
# tenths : 1
=========================================================================
CPU : 2.36 / 2.84 s | Elapsed : 2.00 / 3.00 s
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Total memory usage is 33320 kilobytes
HDL Compilation Only Log File
Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file c:/users/new_log/smallcntr.vhd in Library work.
Architecture inside of Entity smallcntr is up to date.
Compiling vhdl file c:/users/new_log/statmach.vhd in Library work.
Architecture inside of Entity statmach is up to date.
Compiling vhdl file c:/users/new_log/tenths.vhd in Library work.
Architecture tenths_a of Entity tenths is up to date.
Compiling vhdl file c:/users/new_log/decode.vhd in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file c:/users/new_log/cnt60.vhd in Library work.
Architecture inside of Entity cnt60 is up to date.
Compiling vhdl file c:/users/new_log/hex2led.vhd in Library work.
Architecture hex2led_arch of Entity hex2led is up to date.
Compiling vhdl file c:/users/new_log/stopwatch.vhd in Library work.
Architecture inside of Entity stopwatch is up to date.
CPU : 0.23 / 0.47 s | Elapsed : 0.00 / 0.00 s
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Total memory usage is 31272 kilobytes
9-18 Xilinx Development System