Xilinx Synthesis Technology User Guide

XST User Guide
---- General Options
Optimization Criterion : area
Optimization Effort : 1
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file c:/users/new_log/smallcntr.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/statmach.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/tenths.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/decode.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/cnt60.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/hex2led.vhd in Library work.
Entity (Architecture ) compiled.
Compiling vhdl file c:/users/new_log/stopwatch.vhd in Library work.
Entity (Architecture ) compiled.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity (Architecture ).
WARNING:Xst:766 - c:/users/new_log/stopwatch.vhd (Line 68). Generating a
Black Box
for component .
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
Entity analyzed. Unit generated.
9-14 Xilinx Development System