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Xilinx Synthesis Technology User Guide

Xilinx Synthesis Technology User Guide

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Quiet Mode<br />

Timing Report<br />

Log File Analysis<br />

By specifying the -quiet switch at the command line, you can limit the<br />

number of messages that are printed to stdout (computer screen).<br />

Normally, XST will print the entire log to stdout. In quiet mode, XST<br />

will not print the following portions of the log to stdout:<br />

• Copyright Message<br />

• Table Of Contents<br />

• <strong>Synthesis</strong> Options Summary<br />

• The following portions of the Final Report<br />

♦ Final Results header for CPLDs<br />

♦ Final Results section for FPGAs<br />

♦ The following note in the Timing Report<br />

NOTE: THESE TIMING NUMBERS ARE ONLY A<br />

SYNTHESIS ESTIMATE. FOR ACCURATE TIMING<br />

INFORMATION PLEASE REFER TO THE TRACE<br />

REPORT GENERATED AFTER PLACE-AND-ROUTE.<br />

♦ Timing Detail<br />

♦ CPU (XST run time)<br />

♦ Memory usage<br />

Note Device Utilization Summary, Clock Information, and<br />

Timing Summary, will still be available for FPGAs.<br />

At the end of the synthesis, XST reports the timing information for<br />

the design. The report shows the information for all four possible<br />

domains of a netlist: "register to register", "input to register", "register<br />

to outpad" and "inpad to outpad".<br />

See the TIMING REPORT section of the example given in the “FPGA<br />

Log File” section for an example of timing report sections in the XST<br />

log.<br />

XST <strong>User</strong> <strong>Guide</strong> 9-3

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