Xilinx Synthesis Technology User Guide

XST User Guide
• HDL Synthesis (contains HDL Synthesis Report)
During this step, XST tries to recognize as many macros as
possible to create a technology specific implementation. This is
done on a block by block basis. At the end of this step XST gives
an HDL Synthesis Report. This report contains a summary of
recognized macros in the overall design, sorted by macro type.
See the “HDL Coding Techniques” chapter for more details about
the processing of each macro and the corresponding messages
issued during the synthesis process.
• Low Level Synthesis
During this step XST reports the potential removal of equivalent
flip-flops, register replication, etc.
For more information, see the “Log File Analysis” section of the
“FPGA Optimization” chapter.
• Final Report
The Final report is different for FPGA and CPLD flows as
follows.
♦ FPGA and CPLD: includes the output file name, output
format, target family and cell usage.
♦ FPGA only: In addition to the above, the report includes the
following information for FPGAs.
- Device Utilization summary, where XST estimates the
number of slices, gives the number of FFs, IOBs, BRAMS, etc.
This report is very close to the one produced by MAP.
- Clock Information: gives information about the number of
clocks in the design, how each clock is buffered and how
many loads it has.
- Timing report. contains Timing Summary and Detailed
Timing Report. For more information, see the “Log File
Analysis” section of the “FPGA Optimization” chapter.
Note If a design contains encrypted modules, XST hides the
information about these modules.
9-2 Xilinx Development System