Xilinx Synthesis Technology User Guide

Case 2
Command Line Mode
Each design block is located in a separate Verilog file.
1. Create a new directory named vlg_m.
2. Copy the watchver design files from the ISEexamples\watchver
directory of the ISE installation directory to the newly created
vlg_m directory.
To synthesize the design, which is now represented by four Verilog
files, you can use the project approach supported in XST. A Verilog
project file contains a set of "include" Verilog statements (one each per
Verilog module). The order of the files in the project is not important.
XST is able to recognize the hierarchy and compile Verilog files in the
correct order. Moreover, XST automatically detects the top level
module for synthesis.
For our example:
1. Open a new file, called watchver.v.
2. Enter the names of the Verilog files into this file in any order and
save it:
`include "decode.v"
`include "statmach.v"
`include "stopwatch.v"
`include "cnt60.v"
`include "smallcntr.v"
`include "hex2led.v"
3. To synthesize the design, execute the following command from
the XST shell or via a script file:
run -ifn watchver.v -ifmt Verilog -ofn
watchver.ngc -ofmt NGC -p xcv50-bg256-6
-opt_mode Speed -opt_level 1
If you want to synthesize just HEX2LED and check its performance
independently of the other blocks, you can specify the top level
module to synthesize in the command line, using the -top option
(please refer to Table 8-3 for more information):
run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1 -top HEX2LED
XST User Guide 8-23