Xilinx Synthesis Technology User Guide

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XST User Guide Script Mode It can be very tedious work entering XST commands directly into the XST shell, especially when you have to specify several options and execute the same command several times. You can run XST in a script mode as follows. 1. Open a new file called xst.scr in the current directory. Put the previously executed XST shell command into this file and save it. run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1 2. From the tcsh or other shell, enter the following command to start synthesis. xst -ifn xst.scr During this run, XST creates the following files: • watchvhd.ngc: an NGC file ready for the implementation tools • xst.srp: the xst script log file You can improve the readability of the xst.scr file, especially if you use many options to run synthesis. You can place each option with its value on a separate line, respecting the following rules: • The first line must contain only the run command without any options. • There must be no empty lines in the middle of the command • Each line (except the first one) must start with a dash (-) For the previously used command, you may have the xst.cmd file in the following form: run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1 8-22 Xilinx Development System
Case 2 Command Line Mode Each design block is located in a separate Verilog file. 1. Create a new directory named vlg_m. 2. Copy the watchver design files from the ISEexamples\watchver directory of the ISE installation directory to the newly created vlg_m directory. To synthesize the design, which is now represented by four Verilog files, you can use the project approach supported in XST. A Verilog project file contains a set of "include" Verilog statements (one each per Verilog module). The order of the files in the project is not important. XST is able to recognize the hierarchy and compile Verilog files in the correct order. Moreover, XST automatically detects the top level module for synthesis. For our example: 1. Open a new file, called watchver.v. 2. Enter the names of the Verilog files into this file in any order and save it: ìnclude "decode.v" ìnclude "statmach.v" ìnclude "stopwatch.v" ìnclude "cnt60.v" ìnclude "smallcntr.v" ìnclude "hex2led.v" 3. To synthesize the design, execute the following command from the XST shell or via a script file: run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1 If you want to synthesize just HEX2LED and check its performance independently of the other blocks, you can specify the top level module to synthesize in the command line, using the -top option (please refer to Table 8-3 for more information): run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1 -top HEX2LED XST User Guide 8-23
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
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Log File Analysis FPGA Optimization
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FPGA Optimization • Tristates Thi
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FPGA Optimization NOTE: THESE TIMIN
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FPGA Optimization The start point a
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FPGA Optimization If the box_type a
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Instantiation of MUXF5 FPGA Optimiz
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Specifying INITs and RLOCs in HDL C
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FPGA Optimization for registers onl
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PCI Flow FPGA Optimization To succe
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CPLD Optimization This chapter cont
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Implementation Details for Macro Ge
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CPLD Optimization • Final results
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CPLD Optimization The CPLD fitter m
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Design Constraints Chapter 5 This c
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Synthesis Options Design Constraint
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Design Constraints Figure 5-4 Synth
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• Mux Extraction • Mux Style
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Design Constraints For FPGA device
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XST Constraint File (XCF) Design Co
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Design Constraints Timing Constrain
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Design Constraints • Add IO Buffe
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Design Constraints the components c
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HDL Constraints Design Constraints
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FPGA Constraints (non-timing) Desig
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Design Constraints • Number of Cl
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Design Constraints This constraint
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Timing Constraints Design Constrain
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Design Constraints See the “CLOCK
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Design Constraints The following ti
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Design Constraints • TIMEGRP TIME
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Design Constraints See the “INPAD
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Constraint Name clock_buffer bufgdl
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Constraint Name move_last- _stage m
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Constraint Name xor_collapse yes, n
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Constraint Name synthesis/ synopsis
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Design Constraints The following ta
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*Also Supported in XCF format. Impl
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Design Constraints The binary equiv
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Table 5-5 Third Party Constraints N
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Table 5-5 Third Party Constraints N
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Constraints Precedence Design Const
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VHDL Language Support Chapter 6 Thi
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VHDL Language Support 'W' means wea
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VHDL Language Support compiled in t
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Record Types Objects in VHDL MATRIX
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Entity Declaration VHDL Language Su
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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VHDL Reserved Words The following t
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Verilog Language Support Chapter 7
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Behavioral Verilog Features Verilog
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Verilog Language Support Example 7-
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Table 7-1 Expressions Bitwise Negat
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Modules Verilog Language Support In
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Procedural Assignments Verilog Lang
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Page 445 and 446: Analyzing Entity (Architecture ).
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Page 449 and 450: XST Naming Conventions This appendi
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