Xilinx Synthesis Technology User Guide

XST User Guide
• hex2led.v
This design contains seven modules:
• stopwatch
• statmach
• tenths (a CORE Generator core)
• decode
• cnt60
• smallcntr
• HEX2LED
Case 1: All Design Blocks in a Single File
All design blocks will be located in a single Verilog file.
1. Create a new directory called vlg_s.
2. Copy the following files from the ISEexamples\watchver
directory of the ISE installation directory to the newly created
vlg_s directory.
3. Copy and paste the contents of the files into a single file called
'watchver.ver'. Make sure the contents of 'stopwatch.v' appear
last in the file.
To synthesize this design for Speed with optimization effort 1 (Low),
execute the following command:
run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1
Note All options in this command except -opt_mode and -opt_level
are mandatory. Default values are used for all other options.
This command can be launched in two ways:
• Directly from the XST shell
• Script mode
8-20 Xilinx Development System