Xilinx Synthesis Technology User Guide

Command Line Mode
Sometimes, XST is not able to recognize the order and issues the
following message.
WARNING:XST:3204. The sort of the vhdl files
failed, they will be compiled in the order of
the project file.
In this case you must do the following:
• Put all VHDL files in the correct order.
• Add at the end of the list on a separate line the keyword "nosort".
XST will then use your predefined order during the compilation
step.
statmach.vhd
decode.vhd
smallcntr.vhd
cnt60.vhd
hex2led.vhd
stopwatch.vhd
nosort
Example 2: How to Synthesize Verilog Designs
Using Command Line Mode
The goal of this example is to synthesize a hierarchical Verilog design
for a Virtex FPGA using Command Line Mode.
Two main cases are considered:
• All design blocks (modules) are located in a single Verilog file.
• Each design block (module) is located in a separate Verilog file.
Example 2 uses a Verilog design, called watchver. These files can be
found in the ISEexamples\watchver directory of the ISE installation
directory.
• stopwatch.v
• statmach.v
• decode.v
• cnt60.v
• smallcntr.v
XST User Guide 8-19