Xilinx Synthesis Technology User Guide

XST User Guide
VHDL files in the correct order. Moreover, XST automatically detects
the top level block for synthesis.
For the example, perform the following steps:
1. Open a new file, called watchvhd.prj
2. Enter the names of the VHDL files in any order into this file and
save the file:
statmach.vhd
decode.vhd
stopwatch.vhd
cnt60.vhd
smallcntr.vhd
hex2led.vhd
3. To synthesize the design, execute the following command from
XST shell or via script file:
run -ifn watchvhd.prj -ifmt VHDL -ofn watchvhd.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1
If you want to synthesize just "hex2led" and check its performance
independently of the other blocks, you can specify the top level entity
to synthesize in the command line, using the -ent option (please refer
to Table 8-2 for more details):
run -ifn watchvhd.prj -ifmt VHDL -ofn watchvhd.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1 -ent hex2led
During VHDL compilation, XST uses the library "work" as the
default. If some VHDL files must be compiled to different libraries,
then you can add the name of the library just before the file name.
Suppose that "hexl2led" must be compiled into the library, called
"my_lib", then the project file must be:
statmach.vhd
decode.vhd
stopwatch.vhd
cnt60.vhd
smallcntr.vhd
my_lib hex2led.vhd
8-18 Xilinx Development System