Xilinx Synthesis Technology User Guide

XST User Guide
Example 1: How to Synthesize VHDL Designs Using
Command Line Mode
The goal of this example is to synthesize a hierarchical VHDL design
for a Virtex FPGA using Command Line Mode.
Following are the two main cases:
• Case 1—all design blocks (entity/architecture pairs) are located
in a single VHDL file.
• Case 2—each design block (entity/architecture pair) is located in
a separate VHDL file.
The example uses a VHDL design, called watchvhd. The files for
watchvhd can be found in the ISEexamples\watchvhd directory of
the ISE installation directory.
This design contains 7 entities:
• stopwatch
• statmach
• tenths (a CORE Generator core)
• decode
• smallcntr
• cnt60
• hex2led
Case 1: All Blocks in a Single File
For Case 1, all design blocks will be located in a single VHDL file.
1. Create a new directory called vhdl_s.
2. Copy the following files from the ISEexamples\watchvhd
directory of the ISE installation directory to the vhdl_s directory.
♦ stopwatch.vhd
♦ statmach.vhd
♦ decode.vhd
♦ cnt60.vhd
8-14 Xilinx Development System