Xilinx Synthesis Technology User Guide

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XST User Guide Table 8-5 Target Options (9500, 9500XL, 9500XV, XPLA3, CoolRunner-II) Run Command Options Description Values -iobuf Add I/O Buffers Yes, No -pld_mp Macro Preserve Yes, No -pld_xp XOR Preserve Yes, No -keep_hierarchy Keep Hierarchy Yes, No -pld_ce Clock Enable Yes, No -wysiwyg What You See Is What You Get Yes, No Table 8-6 Target Options (Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE) Run Command Options Description Values -bufg Maximum Number of BUFGs created by XST integer - Default 4: Virtex /E, Spartan-II/E - Default 16: Virtex-II/ II Pro -cross_clock_analysis Enable cross clock domain optimization. Yes, No -equivalent_register_removal Equivalent Register Removal Yes, No -glob_opt Global Optimization Goal AllClockNets, Inpad_to_Outpad, Offset_in_Before, Offset_out_after, Max_Delay -iob Pack I/O Registers into IOBs True, False, Auto -iobuf Add I/O Buffers Yes, No -keep_hierarchy Keep Hierarchy Yes, No 8-8 Xilinx Development System
Command Line Mode Table 8-6 Target Options (Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE) Run Command Options Description Values -max_fanout Maximum Fanout integer -Default 500 for Virtex-II and Virtex- II Pro -Default 100 for Virtex, Virtex E, Spartan-II and Spartan-IIE -read_cores Read Cores Yes, No -register_balancing Register Balancing Yes, No, Forward, Backward -move_first_stage Move First Flip-Flop Stage Yes, No -move_last_stage Move Last Flip-Flop Stage Yes, No -register_duplication Register Duplication Yes, No -slice_packing Slice Packing Yes, No -slice_utilization_ratio Slice Utilization Ratio integer (Default 100) -slice_utilization_ratio_maxmargin Slice Utilization Ratio Delta integer (Default 5) The following options have become obsolete for the current version of XST. Table 8-7 Obsolete Run Command Options Run Command Options Description Values -attribfile Constraint File Name file_name -check_attribute_syntax Check Attribute Syntax Yes, No -fsm_fftype FSM Flip-Flop Type D, T -incremental_synthesis Incremental Synthesis Yes, No -macrogen (cpld) Macro Generator Macro+, LogiBLOX, Auto -macrogen (fpga) Macro Generator Macro+ -quiet Suppress Messages to stdout none XST User Guide 8-9
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
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Log File Analysis FPGA Optimization
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FPGA Optimization • Tristates Thi
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FPGA Optimization NOTE: THESE TIMIN
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FPGA Optimization The start point a
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FPGA Optimization If the box_type a
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Instantiation of MUXF5 FPGA Optimiz
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Specifying INITs and RLOCs in HDL C
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FPGA Optimization for registers onl
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PCI Flow FPGA Optimization To succe
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CPLD Optimization This chapter cont
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Implementation Details for Macro Ge
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CPLD Optimization • Final results
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CPLD Optimization The CPLD fitter m
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Design Constraints Chapter 5 This c
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Synthesis Options Design Constraint
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Design Constraints Figure 5-4 Synth
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• Mux Extraction • Mux Style
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Design Constraints For FPGA device
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XST Constraint File (XCF) Design Co
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Design Constraints Timing Constrain
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Design Constraints • Add IO Buffe
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Design Constraints the components c
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HDL Constraints Design Constraints
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FPGA Constraints (non-timing) Desig
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Design Constraints • Number of Cl
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Design Constraints This constraint
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Timing Constraints Design Constrain
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Design Constraints See the “CLOCK
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Design Constraints The following ti
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Design Constraints • TIMEGRP TIME
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Design Constraints See the “INPAD
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Constraint Name clock_buffer bufgdl
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Constraint Name move_last- _stage m
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Constraint Name xor_collapse yes, n
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Constraint Name synthesis/ synopsis
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Design Constraints The following ta
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*Also Supported in XCF format. Impl
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Design Constraints The binary equiv
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Table 5-5 Third Party Constraints N
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Table 5-5 Third Party Constraints N
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Constraints Precedence Design Const
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VHDL Language Support Chapter 6 Thi
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VHDL Language Support 'W' means wea
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VHDL Language Support compiled in t
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Record Types Objects in VHDL MATRIX
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Entity Declaration VHDL Language Su
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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VHDL Language Support Example 6-24
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STANDARD Package VHDL Language Supp
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VHDL Language Support Note Function
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Packages Enumeration Types Integer
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Table 6-4 Objects VHDL Language Sup
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Wait Statement Loop Statement Table
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Page 407 and 408: Command Line Mode Introduction Chap
Page 409 and 410: Command Line Mode • Script File
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Page 421 and 422: ♦ smallcntr.vhd Command Line Mode
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Page 431 and 432: Log File Analysis Introduction This
Page 433 and 434: Quiet Mode Timing Report Log File A
Page 435 and 436: RAM Style : Auto ROM Extraction : y
Page 437 and 438: Synthesizing Unit . Related source
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Page 441 and 442: Log File Analysis Data Path: sixty_
Page 443 and 444: CPLD Log File Log File Analysis The
Page 445 and 446: Analyzing Entity (Architecture ).
Page 447 and 448: Log File Analysis =================
Page 449 and 450: XST Naming Conventions This appendi
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