Xilinx Synthesis Technology User Guide

XST User Guide
Table 8-2 VHDL Source Options
Run Command
Options
Description Values
-work_lib Work Library name
-ent Entity Name name
-arch Architecture name
-bus_delimiter Bus Delimiter , [], {}, ()
Table 8-3 Verilog Source Options
Run Command
Options
Description Values
-case Case Upper, Lower, Maintain
-top Top Module name name
-vlgcase Case Implementation Style Full, Parallel, Full-Parallel
-vlgpath Verilog Search Paths Any valid path to directories separate
by spaces, and enclosed in
double quotes (““)
-vlgincdir Verilog Include Directories Any valid path to directories separate
by spaces, and enclosed in
double quotes (““)
-verilog2001 Verilog 2001 Yes, No
8-6 Xilinx Development System