Xilinx Synthesis Technology User Guide

Verilog Reserved Keywords
Verilog Language Support
The following table shows the Verilog reserved keywords.
Table 7-11 Verilog Reserved Keywords.
always end ifnone noshowcancelled*
repeat tranif1
and endcase incdir* not rnmos tri
assign endconfig* include* notif0 rpmos tri0
automatic endfunction initial notif1 rtran tri1
begin endgenerate* inout or rtranif0 triand
buf endmodule input output rtranif1 trior
bufif0 endprimitive instance* parameter scalared trireg
bufif1 endspecify instance* pmos showcancelled*
use*
case endtable integer posedge signed vectored
casex endtask join primitive small wait
casez event large pull0 specify wand
cell* for liblist* pull1 specparam weak0
cmos force library* pullup strong0 weak1
config* forever localparam* pulldown strong1 while
deassign fork macromodule pulsestyle_ondetect*
supply0 wire
default function medium pulsestyle_onevent*
supply1 wor
defparam generate* module rcmos table xnor
design* genvar* nand real task xor
disable highz0 negedge realtime time
edge highz1 nmos reg tran
else if nor release tranif0
* These keywords are reserved by Verilog, but not supported by XST.
XST User Guide 7-41