Xilinx Synthesis Technology User Guide

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XST User Guide Table 7-6 Procedural Assignments if Statement if, if else Supported case Statement case, casex, casez Supported forever Statement Unsupported repeat Statement Supported (repeat value must be constant) while Statement Supported for Statement Supported (bounds must be static) fork/join Statement Unsupported Timing Control on Procedural Assignments delay (#) Ignored event (@) Unsupported wait Unsupported named events Unsupported Sequential Blocks Supported Parallel Blocks Unsupported Specify Blocks Ignored initial Statement Ignored always Statement Supported task Supported (Recursion Unsupported) functions Supported (Recursion Unsupported) disable Statement Unsupported Table 7-7 System Tasks and Functions System Tasks Ignored System Functions Unsupported 7-38 Xilinx Development System
Table 7-8 Design Hierarchy Module definition Supported Macromodule definition Unsupported Hierarchical names Unsupported defparam Supported Array of instances Unsupported Table 7-9 Compiler Directives `celldefine èndcelldefine Ignored `default_nettype Supported `define Supported ùndef, ìndef, èlsif, Supported ìfdef èlse èndif Supported ìnclude Supported `resetall Ignored `timescale Ignored ùnconnected_drive `nounconnected_drive Verilog Language Support Ignored ùselib Unsupported `file, `line Supported XST User Guide 7-39
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Xilinx Synthesis Technology (XST) U
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About This Manual Manual Contents T
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Resource Description/URL About This
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Conventions Typographical This manu
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Contents About This Manual Conventi
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Contents 8-bit Shift-Left Register
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Contents Dividers .................
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Contents Verilog Flow: ............
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Contents Sequential Process with a
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Introduction Architecture Support X
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Introduction 4. Set the desired Syn
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Figure 1-1 View Synthesis Report In
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HDL Coding Techniques This chapter
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HDL Coding Techniques The following
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Table 2-1 VHDL and Verilog Examples
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Signed/Unsigned Support Registers H
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Flip-flop with Positive-Edge Clock
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VHDL Code HDL Coding Techniques Fol
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IO Pins Description CE Clock Enable
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Log File HDL Coding Techniques The
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HDL Coding Techniques Verilog Code
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HDL Coding Techniques 4-bit Latch w
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Tristates Log File HDL Coding Techn
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Counters HDL Coding Techniques XST
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HDL Coding Techniques 4-bit Unsigne
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HDL Coding Techniques entity counte
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Verilog Code HDL Coding Techniques
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HDL Coding Techniques 4-bit Unsigne
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Accumulators HDL Coding Techniques
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HDL Coding Techniques • shift mod
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HDL Coding Techniques 8-bit Shift-L
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Dynamic Shift Register module shift
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library IEEE; use IEEE.std_logic_11
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neither Full nor Parallel module no
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Related Constraints Related constra
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HDL Coding Techniques entity mux is
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Decoders Log File HDL Coding Techni
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VHDL (One-Cold) Following is the VH
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VHDL Following is the VHDL code. li
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Priority Encoders Log File HDL Codi
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Verilog Logical Shifters HDL Coding
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Example 1 HDL Coding Techniques The
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Verilog Arithmetic Operations Follo
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Unsigned 8-bit Adder HDL Coding Tec
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HDL Coding Techniques Verilog Follo
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Simple Signed 8-bit Adder HDL Codin
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Unsigned 8-bit Adder/Subtractor HDL
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Comparators (=, /=,=) HDL Coding Te
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HDL Coding Techniques this, XST can
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Dividers HDL Coding Techniques VHDL
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B C A OPER +/- RES OPER X8984 HDL C
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HDL Coding Techniques • RAM descr
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HDL Coding Techniques entity raminf
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HDL Coding Techniques VHDL The foll
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HDL Coding Techniques Verilog The f
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HDL Coding Techniques VHDL The foll
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VHDL Following is the VHDL code for
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HDL Coding Techniques Single-Port R
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Verilog HDL Coding Techniques Follo
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HDL Coding Techniques Single-Port R
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Verilog Following is the Verilog co
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VHDL HDL Coding Techniques Followin
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Dual-Port RAM with Asynchronous Rea
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HDL Coding Techniques Dual-Port RAM
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HDL Coding Techniques architecture
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HDL Coding Techniques Dual-Port RAM
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VHDL Following is the VHDL code for
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Inputs Next State Function RESET CL
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FSM with 1 Process HDL Coding Techn
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Inputs FSM with 2 Processes HDL Cod
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process2 : process (state, x1) begi
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State Registers HDL Coding Techniqu
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Compact HDL Coding Techniques Compa
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Black Box Support Log File HDL Codi
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FPGA Optimization Introduction This
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Macro Generation • Number of Cloc
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Multiplexers FPGA Optimization For
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RAMs FPGA Optimization Two types of
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Flip-Flop Retiming FPGA Optimizatio
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FPGA Optimization INCREMENTAL_SYNTH
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FPGA Optimization Note In the curre
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FPGA Optimization generated NGC fil
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FPGA Optimization The problem most
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Log File Analysis FPGA Optimization
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FPGA Optimization • Tristates Thi
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FPGA Optimization NOTE: THESE TIMIN
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FPGA Optimization The start point a
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FPGA Optimization If the box_type a
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Instantiation of MUXF5 FPGA Optimiz
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Specifying INITs and RLOCs in HDL C
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FPGA Optimization for registers onl
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PCI Flow FPGA Optimization To succe
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CPLD Optimization This chapter cont
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Implementation Details for Macro Ge
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CPLD Optimization • Final results
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CPLD Optimization The CPLD fitter m
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Design Constraints Chapter 5 This c
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Synthesis Options Design Constraint
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Design Constraints Figure 5-4 Synth
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• Mux Extraction • Mux Style
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Design Constraints For FPGA device
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XST Constraint File (XCF) Design Co
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Design Constraints Timing Constrain
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Design Constraints • Add IO Buffe
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Design Constraints the components c
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HDL Constraints Design Constraints
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FPGA Constraints (non-timing) Desig
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Design Constraints • Number of Cl
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Design Constraints This constraint
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Timing Constraints Design Constrain
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Design Constraints See the “CLOCK
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Design Constraints The following ti
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Design Constraints • TIMEGRP TIME
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Design Constraints See the “INPAD
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Constraint Name clock_buffer bufgdl
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Constraint Name move_last- _stage m
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Constraint Name xor_collapse yes, n
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Constraint Name synthesis/ synopsis
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Design Constraints The following ta
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*Also Supported in XCF format. Impl
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Design Constraints The binary equiv
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Table 5-5 Third Party Constraints N
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Table 5-5 Third Party Constraints N
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Constraints Precedence Design Const
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VHDL Language Support Chapter 6 Thi
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VHDL Language Support 'W' means wea
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VHDL Language Support compiled in t
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Record Types Objects in VHDL MATRIX
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Entity Declaration VHDL Language Su
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VHDL Language Support Example 6-2 g
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VHDL Language Support Example 6-3 4
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egin Y 13), port map (X,Y,C1); C2
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VHDL Language Support Example 6-5 M
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VHDL Language Support Example 6-8 N
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Example 6-10 Combinatorial Process
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VHDL Language Support Example 6-12
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For...Loop Statement VHDL Language
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Sequential Process without a Sensit
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egin if RST = '1' then DO
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Multiple Wait Statements Descriptio
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Functions and Procedures VHDL Langu
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Page 353 and 354: STANDARD Package VHDL Language Supp
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Page 357 and 358: Packages Enumeration Types Integer
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Page 361 and 362: Wait Statement Loop Statement Table
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Page 365 and 366: Verilog Language Support Chapter 7
Page 367 and 368: Behavioral Verilog Features Verilog
Page 369 and 370: Verilog Language Support Example 7-
Page 371 and 372: Table 7-1 Expressions Bitwise Negat
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Page 375 and 376: Procedural Assignments Verilog Lang
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Page 379 and 380: While Loops Verilog Language Suppor
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Page 389 and 390: Blocking Versus Non-Blocking Proced
Page 391 and 392: Include Files Verilog Language Supp
Page 393 and 394: Verilog Language Support Each insta
Page 395 and 396: Parameters Verilog Language Support
Page 397 and 398: Verilog Language Support • Design
Page 399 and 400: Verilog Meta Comments Verilog Langu
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Page 407 and 408: Command Line Mode Introduction Chap
Page 409 and 410: Command Line Mode • Script File
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Page 413 and 414: Table 8-4 HDL Options (VHDL and Ver
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Page 417 and 418: Command Line Mode • To get a list
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Page 421 and 422: ♦ smallcntr.vhd Command Line Mode
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Page 425 and 426: Command Line Mode Sometimes, XST is
Page 427 and 428: XST Shell Command Line Mode To use
Page 429 and 430: Case 2 Command Line Mode Each desig
Page 431 and 432: Log File Analysis Introduction This
Page 433 and 434: Quiet Mode Timing Report Log File A
Page 435 and 436: RAM Style : Auto ROM Extraction : y
Page 437 and 438: Synthesizing Unit . Related source
Page 439 and 440: # Counters : 2 # 4-bit up counter :
Page 441 and 442: Log File Analysis Data Path: sixty_
Page 443 and 444: CPLD Log File Log File Analysis The
Page 445 and 446: Analyzing Entity (Architecture ).
Page 447 and 448: Log File Analysis =================
Page 449 and 450: XST Naming Conventions This appendi
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