Xilinx Synthesis Technology User Guide

XST User Guide
Note When using VHDL, for a positive-edge clock instead of using
if (C’event and C=’1’) then
you can also use
if (rising_edge(C)) then
and for a negative-edge clock you can use
if (falling_edge(C)) then
or
C’event and C=’0’
Verilog Code
Following is the equivalent Verilog code sample for the flip-flop with
a positive-edge clock.
module flop (C, D, Q);
input C, D;
output Q;
reg Q;
always @(posedge C)
begin
Q = D;
end
endmodule
Flip-flop with Negative-Edge Clock and
Asynchronous Clear
The following figure shows a flip-flop with negative-edge clock and
asynchronous clear.
D
C
CLR
FDC_1
Q
X3847
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