Xilinx Synthesis Technology User Guide

XST User Guide
Verilog Limitations in XST
This section describes Verilog limitations in XST support for case
sensitivity, and blocking and nonblocking assignments.
Case Sensitivity
XST supports case sensitivity as follows:
• Designs can use case equivalent names for I/O ports, nets, regs
and memories.
• Equivalent names are renamed using a postfix ("rnm").
• A rename construct is generated in the NGC file.
• Designs can use Verilog identifiers that differ only in case. XST
will rename them using a postfix as with equivalent names.
Following is an example.
module upperlower4 (input1, INPUT1, output1,
output2);
input input1;
input INPUT1;
For the above example, INPUT1 will be renamed to
INPUT1_rnm0.
The following restrictions apply for Verilog within XST:
• Designs using equivalent names (named blocks, tasks, and
functions) are rejected.
Example:
...
always @(clk)
begin: fir_main5
reg [4:0] fir_main5_w1;
reg [4:0] fir_main5_W1;
This code generates the following error message:
ERROR:Xst:863 - "design.v", line 6: Name
conflict ( and
)
7-32 Xilinx Development System