Xilinx Synthesis Technology User Guide

Parameters
Verilog Language Support
Verilog modules support defining constants known as parameters
which can be passed to module instances to define circuits of
arbitrary widths. Parameters form the basis of creating and using
parameterized blocks in a design to achieve hierarchy and stimulate
modular design techniques. The following is an example of the use of
parameters. Null string parameters are not supported.
Example 7-13 Using Parameters
module lpm_reg (out, in, en, reset, clk);
parameter SIZE = 1;
input in, en, reset, clk;
output out;
wire [SIZE-1 : 0] in;
reg [SIZE-1 : 0] out;
always @(posedge clk or negedge reset)
begin
if (!reset) out