Xilinx Synthesis Technology User Guide

XST User Guide
Example 7-12 Structural Instantiation of Register and BUFG
module foo (sysclk, in, reset,out);
input sysclk, in, reset;
output out;
reg out;
wire sysclk_out;
FDC register (sysclk, reset, in, out); //position based
//referencing
BUFG clk (.O(sysclk_out), .I(sysclk)); //name based referencing
….
endmodule
The unisim_comp.v library file supplied with XST, includes the
definitions for FDC and BUFG.
module FDC ( C, CLR, D, Q);
input C;
input CLR;
input D;
output Q;
endmodule
// synthesis attribute BOX_TYPE of FDC is "BLACK_BOX"
module BUFG ( O, I);
output O;
input I;
endmodule
// synthesis attribute BOX_TYPE of BUFG is "BLACK_BOX"
7-30 Xilinx Development System