Xilinx Synthesis Technology User Guide

Verilog Language Support
Each instance of the built-in modules has a unique instantiation name
such as a_inv, b_inv, out. The wiring up of the gates describes an
XOR gate in structural Verilog.
Example 7-11 gives the structural description of a half adder
composed of four, 2 input nand modules.
Example 7-11 Structural Description of a Half Adder
module halfadd (X, Y, C, S);
input X, Y;
output C, S;
wire S1, S2, S3;
nand NANDA (S3, X, Y);
nand NANDB (S1, X, S3);
nand NANDC (S2, S3, Y);
nand NANDD (S, S1, S2);
assign C = S3;
endmodule
X
Y
A
B
NANDA
Y
Figure 7-1 Synthesized Top Level Netlist
The structural features of Verilog HDL also allow you to design
circuits by instantiating pre-defined primitives such as gates,
registers and Xilinx specific primitives like CLKDLL and BUFGs.
These primitives are other than those included in the Verilog
language. These pre-defined primitives are supplied with the XST
Verilog libraries (unisim_comp.v).
XST User Guide 7-29
S3
A
B
A
B
NANDB
NANDC
Y
Y
S1
S2
A
B
NANDD
Y
S
C
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