Xilinx Synthesis Technology User Guide

XST User Guide
Structural Verilog Features
Structural Verilog descriptions assemble several blocks of code and
allow the introduction of hierarchy in a design. The basic concepts of
hardware structure are the module, the port and the signal. The
component is the building or basic block. A port is a component I/O
connector. A signal corresponds to a wire between components.
In Verilog, a component is represented by a design module. The
module declaration provides the "external" view of the component; it
describes what can be seen from the outside, including the
component ports. The module body provides an "internal" view; it
describes the behavior or the structure of the component.
The connections between components are specified within
component instantiation statements. These statements specify an
instance of a component occurring within another component or the
circuit. Each component instantiation statement is labeled with an
identifier. Besides naming a component declared in a local
component declaration, a component instantiation statement
contains an association list (the parenthesized list) that specifies
which actual signals or ports are associated with which local ports of
the component declaration.
The Verilog language provides a large set of built-in logic gates which
can be instantiated to build larger logic circuits. The set of logical
functions described by the built-in gates include AND, OR, XOR,
NAND, NOR and NOT.
Here is an example of building a basic XOR function of two single bit
inputs a and b.
module build_xor (a, b, c);
input a, b;
output c;
wire c, a_not, b_not;
not a_inv (a_not, a);
not b_inv (b_not, b);
and a1 (x, a_not, b);
and a2 (y, b_not, a);
or out (c, x, y);
endmodule
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