Xilinx Synthesis Technology User Guide

XST User Guide
Constants, Macros, Include Files and Comments
This section discusses constants, macros, include files, and
comments.
Constants
By default, constants in Verilog are assumed to be decimal integers.
They can be specified explicitly in binary, octal, decimal, or
hexadecimal by prefacing them with the appropriate syntax. For
example, 4’b1010, 4’o12, 4’d10 and 4’ha all represent the same value.
Macros
Verilog provides a way to define macros as shown in the following
example.
`define TESTEQ1 4’b1101
Later in the design code a reference to the defined macro is made as
follows.
if (request == `TESTEQ1)
This is shown in the following example.
`define myzero 0
assign mysig = `myzero;
Verilog provides the `ifdef and `endif constructs to determine
whether a macro is defined or not. These constructs are used to define
conditional compilation. If the macro called out by the `ifdef
command has been defined, that code will be compiled. If not, the
code following the `else command is compiled. The `else is not
required, but the `endif must complete the conditional statement. The
`ifdef and `endif constructs are shown in the following example.
`ifdef MYVAR
module if_MYVAR_is_declared;
...
endmodule
`else
module if_MYVAR_is_not_declared;
...
endmodule
`endif
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