Xilinx Synthesis Technology User Guide

XST User Guide
Assignment Extension Past 32 Bits
If the expression on the left-hand side of an assignment is wider than
the expression on the right-hand side, the left-hand side will be
padded to the left according to the following rules.
• If the right-hand expression is signed, the left-hand expression
will be padded with the sign bit (0 for positive, 1 for negative, z
for high impedance or x for unknown).
• If the right-hand expression is unsigned, the left-hand expression
will be padded with 0s.
• For unsized x or z constants only the following rule applies. If the
value of the right-hand expression’s left-most bit is z (high
impedance) or x (unknown), regardless of whether the righthand
expression is signed or unsigned, the left-hand expression
will be padded with that value (z or x, respectively).
Note The above rules follow the Verilog-2001 standard, and are not
backward compatible with Verilog-1995.
Tasks and Functions
The declaration of a function or task is intended for handling blocks
used multiple times in a design. They must be declared and used in a
module. The heading part contains the parameters: input parameters
(only) for functions and input/output/inout parameters for tasks.
The return value of a function can be declared either signed or
unsigned. The content is similar to the combinatorial always block
content. Recursive function and task calls are not supported.
Example 7-9 shows a function declared within a module. The ADD
function declared is a single-bit adder. This function is called 4 times
with the proper parameters in the architecture to create a 4-bit adder.
The same example, described with a task, is shown in Example 7-10.
7-22 Xilinx Development System