Xilinx Synthesis Technology User Guide

Verilog Language Support
• You cannot assign a bit/part select of a signal through an assign /
deassign statement. For example, the following design will be
rejected:
module assig (RST, SELECT, STATE,
CLOCK,DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:7] DATA_IN;
output [0:7] STATE;
reg [0:7] STATE;
always @ (RST) // block b1
if(RST)
begin
assign STATE[0:7] = 8'b0;
end else
begin
deassign STATE[0:7];
end
always @ (posedge CLOCK) // block b2
begin
if (SELECT)
STATE [0:3]= DATA_IN[0:3];
else
STATE [4:7]= DATA_IN[4:7];
end
XST User Guide 7-21