Xilinx Synthesis Technology User Guide

XST User Guide
• The assign / deassign statement must be performed in the same
always block through an if /else statement. For example, the
following design will be rejected:
module dflop (RST, SET, STATE, CLOCK, DATA_IN);
input RST;
input SET;
input CLOCK;
input DATA_IN;
output STATE;
reg STATE;
always @ (RST or SET) // block b1
case ({RST,SET})
2'b00: assign STATE = 1'b0;
2'b01: assign STATE = 1'b0;
2'b10: assign STATE = 1'b1;
2'b11: deassign STATE;
endcase
always @ (posedge CLOCK) // block b2
begin
STATE = DATA_IN;
end
endmodule
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