Xilinx Synthesis Technology User Guide

XST User Guide
Assign and Deassign Statements
Assign and deassign statements are supported within simple
templates.
The following is an example of the general template for assign /
deassign statements:
module assig (RST, SELECT, STATE, CLOCK, DATA_IN);
input RST;
input SELECT;
input CLOCK;
input [0:3] DATA_IN;
output [0:3] STATE;
reg [0:3] STATE;
always @ (RST)
if(RST)
begin
assign STATE = 4'b0;
end else
begin
deassign STATE;
end
always @ (posedge CLOCK)
begin
STATE = DATA_IN;
end
endmodule
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