Xilinx Synthesis Technology User Guide

Verilog Language Support
Example 7-7 8 Bit Register with Asynchronous Reset (high-true)
Using an Always Block
module EXAMPLE (DI, CLK, RST, DO);
input [7:0] DI;
input CLK, RST;
output [7:0] DO;
reg [7:0] DO;
always @(posedge CLK or posedge RST)
if (RST == 1’b1)
DO = 8’b00000000;
else
DO = DI;
endmodule
The following example describes an 8-bit counter.
Example 7-8 8 Bit Counter with Asynchronous Reset (low-true)
Using an Always Block
module seq2 (CLK, RST, DO);
input CLK, RST;
output [7:0] DO;
reg [7:0] DO;
always @(posedge CLK or posedge RST)
if (RST == 1’b1)
DO = 8’b00000000;
else
DO = DO + 8’b00000001;
endmodule
XST User Guide 7-17