Xilinx Synthesis Technology User Guide

XST User Guide
Sequential Always Blocks
Sequential circuit description is based on always blocks with a
sensitivity list.
The sensitivity list contains a maximum of three edge-triggered
events: the clock signal event (which is mandatory), possibly a reset
signal event, and a set signal event. One, and only one "If...else"
statement is accepted in such an always block.
An asynchronous part may appear before the synchronous part in the
first and the second branch of the "If...else" statement. Signals
assigned in the asynchronous part must be assigned to the constant
values ’0’, ’1’, ’X’ or ’Z’ or any vector composed of these values.
These same signals must also be assigned in the synchronous part
(that is, the last branch of the "if-else" statement). The clock signal
condition is the condition of the last branch of the "if-else" statement.
The following example gives the description of an 8-bit register.
Example 7-6 8 Bit Register Using an Always Block
module seq1 (DI, CLK, DO);
input [7:0] DI;
input CLK;
output [7:0] DO;
reg [7:0] DO;
always @(posedge CLK)
DO = DI ;
endmodule
The following example gives the description of an 8-bit register with
a clock signal and an asynchronous reset signal.
7-16 Xilinx Development System