Xilinx Synthesis Technology User Guide

While Loops
Verilog Language Support
When using always blocks, use the "while" statement to execute
repetitive procedures. A "while" loop executes other statements until
its test expression becomes false. It is not executed if the test
expression is initially false.
• The test expression is any valid Verilog expression.
• To prevent endless loops, use the "-iteration_limit" switch.
The following example shows the use of a While Loop.
Example 7-5 While Loop Description
parameter P = 4;
always @(ID_complete)
begin : UNIDENTIFIED
integer i;
reg found;
unidentified = 0;
i = 0;
found = 0;
while (!found && (i < P))
begin
found = !ID_complete[i];
unidentified[i] = !ID_complete[i];
i = i + 1;
end
end
XST User Guide 7-15