Xilinx Synthesis Technology User Guide

Verilog Language Support
Casez treats all z values in any bit position of the branch alternative
as a don’t care.
Casex treats all x and z values in any bit position of the branch
alternative as a don’t care.
The question mark (?) can be used as a “don’t care” in any of the
preceding case statements. The following example shows how a
MUX can be described using a Case statement.
Example 7-3 MUX Description Using Case Statement
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @(sel or a or b or c or d)
begin
case (sel)
2’b00: outmux = a;
2’b01: outmux = b;
2’b10: outmux = c;
default: outmux = d;
endcase
end
endmodule
The preceding Case statement will evaluate the values of the input sel
in priority order. To avoid priority processing, it is recommended that
you use a parallel-case Verilog meta comment which will ensure
parallel evaluation of the sel inputs as in the following.
Example:
always @(sel or a or b or c or d) //synthesis parallel_case
For and Repeat Loops
When using always blocks, repetitive or bit slice structures can also
be described using the "for" statement or the "repeat" statement.
XST User Guide 7-13